Clock generation circuit and semiconductor memory device employing the same

1. A semiconductor memory device, comprising:

a first internal clock generation circuit configured to generate a first internal clock signal by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device;

a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal;

a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage;

a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal; and

a data output circuit configured to output a data in synchronization with the synchronization clock signal.

2. The semiconductor memory device of claim 1 , wherein the second internal clock generation circuit comprises:

a signal transfer line configured to transfer the first internal clock signal to be outputted as the second internal clock signal; and

a delay control unit configured to control a delay amount of the signal transfer line in response to the control voltage.

3. The semiconductor memory device of claim 1 , wherein the control voltage has a waveform determined corresponding to the profile selection signal.

4. The semiconductor memory device of claim 1 , wherein the control voltage has a voltage level changing in response to the profile selection signal.

5. The semiconductor memory device of claim 1 , wherein the path selection signal is generated in response to an operation frequency of the semiconductor memory device.

6. The semiconductor memory device of claim 1 , wherein the second internal clock generation circuit is activated in response to the path selection signal.

7. The semiconductor memory device of claim 1 , wherein the selection output circuit is configured to output the first internal clock signal as the synchronization clock signal, at a first operation frequency of the semiconductor memory device, and output the second internal clock signal as the synchronization clock signal, at a second operation frequency that is higher than the first operation frequency.

8. The semiconductor memory device of claim 1 , wherein the control voltage generation circuit comprises:

a variable resistance unit configured to vary a resistance value in response to the profile selection signal; and

an output unit configured to output the control voltage having a voltage level corresponding to the resistance value of the variable resistance unit.

9. The semiconductor memory device of claim 8 , wherein the control voltage generation circuit further comprises:

a feedback unit configured to provide the control voltage back to the variable resistance unit.

10. The semiconductor memory device of claim 8 , wherein the resistance value of the variable resistance unit corresponds to the voltage level of the control voltage.

11. The semiconductor memory device of claim 1 , wherein the first internal clock generation circuit comprises a delay locked loop or a phase locked loop.

12. The semiconductor memory device of claim 1 , wherein the control voltage comprises chopping wave swinging between voltage levels determined in response to the profile selection signal.

13. A clock generation circuit, comprising:

a control voltage generation circuit configured to generate a control voltage changing in response to a profile selection signal; and

a voltage controlled delay line configured to generate an internal clock signal by delaying a reference clock signal by a time corresponding to the control voltage,

wherein the control voltage generation circuit comprises:

a variable resistance unit configured to vary a resistance value in response to the profile selection signal; and

an output unit configured to output the control voltage having a voltage level corresponding to the resistance value of the variable resistance unit.

14. The clock generation circuit of claim 13 , wherein the control voltage has a voltage level changing in response to the profile selection signal.

15. The clock generation circuit of claim 13 , wherein the control voltage generation circuit further comprises:

a feedback unit configured provide the control voltage back to the variable resistance unit.

16. The clock generation circuit of claim 13 , wherein the resistance value of the variable resistance unit corresponds to the voltage level of the control voltage.

17. The clock generation circuit of claim 13 , wherein the voltage controlled delay line comprises:

a signal transfer line configured to transfer the reference clock signal to be outputted as the internal clock signal; and

a delay control unit configured to control a delay amount of the signal transfer line in response to the control voltage.

18. The clock generation circuit of claim 13 , wherein the reference clock signal is generated by a delay locked loop or a phase locked loop.

19. The clock generation circuit of claim 13 , wherein the control voltage comprises chopping wave swinging between voltage levels determined in response to the profile selection signal.