Nonvolatile semiconductor memory device
View Patent ↗Bit lines connected to each nonvolatile memory cell are selected by corresponding selective transistors. A first drive circuit for driving the gate of one of the selective transistors receives a voltage selected by a first voltage switch, and a second drive circuit for driving the gate of the other selective transistor receives a voltage selected by a second voltage switch. A transistor constituting the first drive circuit is different in structure from a transistor constituting the second drive circuit.
1. A nonvolatile semiconductor memory device, comprising:
a memory array having a plurality of nonvolatile memory cells arranged using a virtual ground, a word line for control of a gate and first and second bit lines being connected to each of the nonvolatile memory cells;
a first selective transistor group for selecting the first bit line;
a first selective transistor drive circuit configured to drive gates of the first selective transistor group;
a second selective transistor group for selecting the second bit line;
a second selective transistor drive circuit configured to drive gates of the second selective transistor group;
a first voltage switch configured to select a voltage to be supplied to the first selective transistor drive circuit depending on an operation of the memory array; and
a second voltage switch configured to select a voltage to be supplied to the second selective transistor drive circuit depending on the operation of the memory array, wherein
a transistor constituting the first selective transistor drive circuit is different in structure from a transistor constituting the second selective transistor drive circuit.
2. The nonvolatile semiconductor memory device of claim 1 , wherein
during program operation of the memory array, a first voltage is applied to the first selective transistor group from the first voltage switch via the first selective transistor drive circuit, and a second voltage is applied to the second selective transistor group from the second voltage switch via the second selective transistor drive circuit, and
during read operation of the memory array, a third voltage is applied to the first selective transistor group from the first voltage switch via the first selective transistor drive circuit, and a fourth voltage is applied to the second selective transistor group from the second voltage switch via the second selective transistor drive circuit.
3. The nonvolatile semiconductor memory device of claim 2 , wherein
the first voltage is supplied from a first power supply circuit, and the second voltage is supplied from a second power supply circuit.
4. The nonvolatile semiconductor memory device of claim 3 , wherein
the first power supply circuit and the second power supply circuit supply different voltages.
5. The nonvolatile semiconductor memory device of claim 2 , wherein
the first or second voltage whichever is lower is supplied from a power supply circuit that supplies a voltage to be applied to the word line during the read operation.
6. The nonvolatile semiconductor memory device of claim 1 , wherein
the transistor constituting the first selective transistor drive circuit is different in the thickness of a gate oxide film from the transistor constituting the second selective transistor drive circuit.
7. The nonvolatile semiconductor memory device of claim 1 , wherein
the transistor constituting the first selective transistor drive circuit is different in the distance between a gate and a drain contact from the transistor constituting the second selective transistor drive circuit.
8. The nonvolatile semiconductor memory device of claim 1 , wherein
the transistor constituting the first selective transistor drive circuit is different in gate length from the transistor constituting the second selective transistor drive circuit.
9. The nonvolatile semiconductor memory device of claim 1 , wherein
the nonvolatile memory cell is a metal oxide nitride oxide silicon (MONOS) memory cell.
10. The nonvolatile semiconductor memory device of claim 9 , wherein
in the MONOS memory cell, information is stored by injecting charge locally into a portion of the memory cell near a bit line, and one-bit information is stored using a portion of the memory cell near one of the first and second bit lines connected.