Rate matching and de-rate matching on digital signal processors
View Patent ↗Provided are devices, systems and methods for rate matching and de-rate matching on digital signal processors. In one embodiment, a device for rate matching and de-rate matching, includes an interface for receiving a plurality of blocks of data and digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters and receive a set of pre-computed puncturing thresholds. For one or more blocks in the plurality of blocks, the DSP computes a block signature from the pre-computed puncturing thresholds; matches the block signature to one of a set of pre-computed zone signatures, derives a zone index corresponding to the one pre-computed zone signature, and applies pre-computed permutation and puncturing transformations corresponding to the zone index to the block.
1. A system for rate matching and de-rate matching, the system comprising: a memory configured to store a plurality of blocks of data; a digital signal processor (DSP) configured to: pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters; receive a set of pre-computed puncturing thresholds; and for one or more blocks in the plurality of blocks compute a block signature from the pre-computed puncturing thresholds; match the block signature to one of a set of pre-computed zone signatures, derive a zone index corresponding to the one pre-computed zone signature, and apply pre-computed permutation and puncturing transformations corresponding to the zone index to the block.
2. The system of claim 1 , wherein the DSP is further configured to load the block into a vector register after deriving the zone index.
3. The system of claim 2 wherein the DSP is further configured to apply the pre-computed permutation and puncturing transformations to the block in the vector register.
4. The system of claim 3 , wherein the DSP is further configured to write the block in the vector register to the memory.
5. The system of claim 1 , wherein the DSP is further configured to load the block into a vector register after deriving the zone index.
6. The system of claim 5 , wherein the DSP is further configured to pack the block in the vector register from double words to words.
7. The system of claim 6 ; wherein the DSP is further configured to apply the pre-computed permutation and puncturing transformations to the packed block in the vector register.
8. The system of claim 7 , wherein the DSP is further configured to unpack the transformed block in the vector register.
9. The system of claim 8 , wherein the DSP is further configured to write the unpacked transformed block in the vector register to the memory.
10. A device for rate matching and de-rate matching, comprising: an interface for receiving a plurality of blocks of data; digital signal processor configured to: pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters; receive a set of pre-computed puncturing thresholds; and for one or more blocks in the plurality of blocks compute a block signature from the pre-computed puncturing thresholds; match the block signature to one of a set of pre-computed zone signatures, derive a zone index corresponding to the one pre-computed zone signature, apply pre-computed permutation and puncturing transformations corresponding to the zone index to the block.
11. The device of claim 10 , wherein the DSP is further configured to load the block into a vector register after deriving the zone index.
12. The device of claim 11 wherein the DSP is further configured to apply the pre-computed permutation and puncturing transformations to the block in the vector register.
13. The device of claim 12 , wherein the DSP is further configured to write the block in the vector register to a memory.
14. The device of claim 10 , wherein the DSP is further configured to load the block into a vector register after deriving the zone index.
15. The device of claim 14 , wherein the DSP is further configured to pack the block in the vector register from double words to words.
16. The device of claim 15 ; wherein the DSP is further configured to apply the pre-computed permutation and puncturing transformations to the packed block in the vector register.
17. The device of claim 16 , wherein the DSP is further configured to unpack the transformed block in the vector register.
18. The device of claim 17 , wherein the DSP is further configured to write the unpacked transformed block in the vector register to a memory.