IP Library Granted Patent US 8,791,686
Granted Patent B2
US 8,791,686 · App. 13/609,944 · Granted Jul 29, 2014

Constant output reference voltage circuit

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Quick Facts
Patent No.
US 8,791,686
App. No.
13/609,944
Granted
Jul 29, 2014
Kind
B2
Abstract

The voltage reference circuit includes: a first MOS transistor; a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor and having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value and a K value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current; and a fourth MOS transistor having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current.

Claims (2)

1. A voltage reference circuit comprising: a first MOS transistor including a source terminal connected to a first power supply terminal; a second MOS transistor including a source terminal connected to the first power supply terminal and a gate terminal connected to a gate terminal of the first MOS transistor, the second MOS transistor having an absolute value of a threshold value higher than an absolute value of a threshold value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current of the current mirror circuit; a fourth MOS transistor having an absolute value of a threshold value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current of the current mirror circuit, wherein the voltage reference circuit outputs, as a reference voltage, a constant voltage based on the absolute values of the threshold values of the third MOS transistor and the fourth MOS transistor; wherein the current mirror circuit includes: a fifth MOS transistor including a drain terminal and a gate terminal connected to a drain terminal of the first MOS transistor; a sixth MOS transistor including a gate terminal connected to the gate terminal of the fifth MOS transistor and a drain terminal connected to the gate terminal and a drain terminal of the second MOS transistor; a seventh MOS transistor including a gate terminal connected to the gate terminal of the fifth MOS transistor and a drain terminal connected to a drain terminal of the third MOS transistor; an eighth MOS transistor including a gate terminal connected to the gate terminal of the fifth MOS transistor and a drain terminal connected to a drain terminal of the fourth MOS transistor; and a resistor including one terminal connected to a gate terminal of the third MOS transistor and another terminal connected to a gate terminal of the fourth MOS transistor, wherein the voltage reference circuit outputs, as a reference voltage, a constant voltage based on a voltage at both ends of the resistor.

2. A voltage reference circuit comprising: a first MOS transistor including a source terminal connected to a first power supply terminal; a second MOS transistor including a source terminal connected to the first power supply terminal and a gate terminal connected to a gate terminal of the first MOS transistor, the second MOS transistor having an absolute value of a threshold value higher than an absolute value of a threshold value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current of the current mirror circuit; wherein the current mirror circuit includes: a fourth MOS transistor including a drain terminal and a gate terminal connected to a drain terminal of the first MOS transistor; and a fifth MOS transistor including a gate terminal connected to the gate terminal of the fourth MOS transistor and a drain terminal connected to a gate terminal and a drain terminal of the third MOS transistor, wherein the third MOS transistor is configured to include a gate terminal connected to the gate terminal of the second MOS transistor and a source terminal connected to a drain terminal of the second MOS transistor, so that the voltage reference circuit outputs the reference voltage from a connecting point of the source terminal of the third MOS transistor and the drain terminal of the second MOS transistor; and wherein the voltage reference circuit outputs, as a reference voltage, a constant voltage based on the absolute values of the threshold values of the third MOS transistor and the second MOS transistor.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2012
From: YAMASAKI, TARO; UTSUNOMIYA, FUMIYASU
To: SEIKO INSTRUMENTS INC.
Reel/Frame 028937/0931 →