Impedance control circuit and semiconductor device including the same

1. An impedance control circuit, comprising:

a pull-up code generator configured to generate pull-up impedance control codes using a voltage of a first node;

a pull-up impedance unit configured to pull-up-drive the first node in response to the pull-up impedance control codes;

a plurality of dummy impedance units enabled in response to respective select signals and each configured to pull-up-drive a second node in response to the pull-up impedance control codes;

a pull-down code generator configured to generate pull-down impedance control codes using a voltage of the second node; and

a plurality of pull-down impedance units enabled in response to the respective select signals and each configured to pull-down-drive the second node in response to the pull-down impedance control codes.

2. The impedance control circuit of claim 1 , wherein enabled dummy impedance units among the dummy impedance units have the same impedance value determined by the pull-up impedance control codes, and enabled pull-down impedance units among the pull-down impedance units have the same impedance value determined by the pull-down impedance control codes.

3. The impedance control circuit of claim 1 , wherein at least one of the select signals is enabled in response to an output control signal.

4. The impedance control circuit of claim 3 , further comprising a storage circuit configured to store the pull-down impedance control codes generated whenever the number of enabled pull-down impedance units is changed among the pull-down impedance units and selectively output one of the stored pull-down impedance control codes is in response to the output control signal.

5. The impedance control circuit of claim 3 , further comprising a storage circuit configured to store the pull-down impedance control codes generated for each of division calibration times that are obtained by dividing a whole calibration time into the number of the pull-down impedance units and selectively output one of the stored pull-down impedance control codes in response to the output control signal,

wherein an enable period of an A-th select signal (2≦A≦ the number of the pull-down impedance units) is from an end of an A-1-th division calibration time to an end of the whole calibration time.

6. The impedance control circuit of claim 5 , wherein the storage circuit includes:

a plurality of latch stages configured to store the pull-down impedance control codes generated for the respective division calibration times in response to a plurality of latch signals, respectively; and

an output unit configured to selectively output one of the pull-down impedance control codes stored in the latch stages in response to the output control signal.

7. The impedance control circuit of claim 3 , wherein the output control signal includes a mode register set signal.

8. The impedance control circuit of claim I, wherein the pull-up code generator includes:

a pull-up comparator configured to compare a reference voltage with the voltage of the first node to generate a first up/down signal indicating which voltage is higher; and a pull-up counter unit configured to increase/reduce the values of the pull-up impedance control codes in response to the first up/down signal, and

the pull-down code generator includes:

a pull-down comparator configured to compare the reference voltage with the voltage of the second node to generate a second up/down signal indicating which voltage is higher; and a pull-down counter unit configured to increase/reduce the values of the pull-down impedance control codes in response to the second up/down signal.

9. The impedance control circuit of claim 1 , wherein each of the dummy impedance units includes a plurality of resistors that is connected to the second node in parallel and configured to supply a power supply voltage to the second node therethrough in response to the pull-up impedance control codes, and

each of the pull-down impedance units includes a plurality of resistors that is connected to the second node in parallel and configured to supply a ground voltage to the second node therethrough in response to the pull-down impedance control codes.

10. The impedance control circuit of claim 1 , further comprising:

a first selector configured to transmit the pull-up impedance control codes to the plurality of dummy impedance units in response to the respective select signals; and

a second selector configured to transmit the pull-down impedance control codes to the plurality of pull-down impedance units in response to the respective select signals.

11. An impedance control circuit, comprising:

a pull-down code generator configured to generate pull-down impedance control codes using a voltage of a first node;

a pull-down impedance unit configured to pull-down-drive the first node in response to the pull-down impedance control codes;

a plurality of dummy impedance units enabled in response to respective select signals and each configured to pull-down-drive a second node in response to the pull-down impedance control codes;

a pull-up code generator configured to generate pull-up impedance control codes using a voltage of the second node; and

a plurality of pull-up impedance units enabled in response to the respective select signals and each configured to pull-up-drive the second node in response to the pull-up impedance control codes.

12. The impedance control circuit of claim 11 , wherein enabled dummy impedance units among the dummy impedance units have the same impedance value determined by the pull-down impedance control codes, and enabled pull-up impedance units among the pull-up impedance units have the same impedance value determined by the pull-up impedance control codes.

13. The impedance control circuit of claim 11 , wherein at least one of the select signals is enabled in response to an output control signal.

14. The impedance control circuit of claim 13 , further comprising a storage circuit configured to store the pull-up impedance control codes generated whenever the number of enabled pull-up impedance units is changed among the pull-up impedance units and selectively output one of the stored pull-up impedance control codes is in response to the output control signal.

15. The impedance control circuit of claim 13 , further comprising a storage circuit configured to store the pull-up impedance control codes generated for each of division calibration times that are obtained by dividing a whole calibration time into the number of the pull-up impedance units and selectively output one of the stored pull-up impedance control codes in response to the output control signal,

wherein an enable period of an A-th select signal (2≦A≦ the number of the pull-up impedance units) is from an end of an A-1-th division calibration time to an end of the whole calibration time.

16. The impedance control circuit of claim 15 , wherein the storage circuit includes:

a plurality of latch stages configured to store the pull-up impedance control codes generated for the respective division calibration times in response to a plurality of latch signals, respectively; and

an output unit configured to selectively output one of the pull-up impedance control codes stored in the latch stages in response to the output control signal.

17. A semiconductor device, comprising:

an impedance control circuit configured to generate pull-up impedance control codes and pull-down impedance control codes using a voltage of a first node; and

a termination circuit configured to control impedance values of an interface pad in response to the pull-up impedance control codes and the pull-down impedance control codes,

wherein the impedance control circuit includes:

a plurality of dummy impedance units enabled in response to respective select signals.

18. The semiconductor device of claim 17 , wherein the impedance control circuit further includes:

a pull-up code generator configured to generate the pull-up impedance control codes using the voltage of the first node;

a pull-up impedance unit configured to pull-up-drive the first node with an impedance value determined in response to the pull-up impedance control codes;

a pull-down code generator configured to generate the pull-down impedance control codes using a voltage of the second node; and

a plurality of pull-down impedance units enabled in response to the respective select signals, wherein the enabled pull-down impedance units are configured to pull-down-drive the second node with the same impedance value determined in response to the pull-down impedance control codes,

wherein the plurality of dummy impedance units are configured to pull-up-drive a second node with the same impedance value determined in response to the pull-up impedance control codes.

19. The semiconductor device of claim 18 , wherein at least one of the select signals is enabled in response to an output control signal.

20. The semiconductor device of claim 19 , wherein the impedance control circuit further includes a storage circuit configured to store the pull-down impedance control codes generated whenever the number of the enabled pull-down impedance units is changed and selectively output one of the stored pull-down impedance control codes is in response to the output control signal.

21. The semiconductor device of claim 19 , wherein the impedance control circuit further includes a storage circuit configured to store the pull-down impedance control codes generated for each of division calibration times that are obtained by dividing a whole calibration time into the number of the pull-down impedance units and selectively output one of the stored pull-down impedance control codes in response to the output control signal,

wherein an enable period of an A-th select signal (2≦A≦ the number of the pull-down impedance units) is from an end of an A-1-th division calibration time to an end of the whole calibration time.

22. The semiconductor device of claim 21 , wherein the storage circuit includes:

a plurality of latch stages configured to store the pull-down impedance control codes generated for the respective division calibration times in response to a plurality of latch signals, respectively; and

an output unit configured to selectively output one of the pull-down impedance control codes stored in the latch stages in response to the output control signal to the termination circuit.

23. The semiconductor device of claim 17 , wherein the impedance control circuit includes:

a pull-down code generator configured to generate the pull-down impedance control codes using the voltage of the first node;

a pull-down impedance unit configured to pull-down-drive the first node with an impedance value determined in response to the pull-down impedance control codes;

a plurality of dummy impedance units enabled in response to respective select signals, wherein the enabled dummy impedance units are configured to pull-down-drive a second node with the same impedance value determined in response to the pull-down impedance control codes;

a pull-up code generator configured to generate the pull-up impedance control codes using a voltage of the second node; and

a plurality of pull-up impedance units enabled in response to the respective select signals, wherein the enabled pull-up impedance units are configured to pull-up-drive the second node with the same impedance value determined in response to the pull-up impedance control codes.

24. The semiconductor device of claim 17 , wherein the first node includes a ZQ node to which an external resistor is connected.