SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Semiconductor devices and methods of fabricating semiconductor devices are provided. Two or more layers can be formed on a silicon substrate, wherein one or more of the layers are used for controlling an isolation recess. A first layer can comprise a first material and a second layer can comprise a second material.
1 . A semiconductor structure, comprising:
a semiconductor substrate comprising a plurality of fins;
a multi-layer structure over the semiconductor substrate, the multi-layer structure comprises a first layer and at least a second layer, the first layer comprises a first material and the second layer comprises a second material different from the first material; and
an epitaxial source/drain portion, wherein the second layer is formed on the first layer and contacts a bottom of the epitaxial source/drain portion.
2 . The semiconductor structure of claim 1 , wherein the first material comprises silicon dioxide (SiO2) and the second material comprises silicon nitride (SiN).
3 . The semiconductor structure of claim 1 , wherein the first layer and the second layer comprise a similar thickness.
4 . The semiconductor structure of claim 1 , wherein the first layer comprises a first thickness and the second layer comprises a second thickness, wherein the first thickness is greater than the second thickness.
5 . The semiconductor structure of claim 1 , wherein the first layer and the second layer are local isolation layers.
6 . A semiconductor structure, comprising:
a semiconductor substrate comprising a plurality of fins;
a replacement metal gate region; and
a multi-layer structure over the semiconductor substrate, the multi-layer structure comprises a first layer, a second layer, and at least a third layer, wherein the first layer and the third layer comprise a first material and the second layer comprises a second material different from the first material,
and wherein the second layer is formed between the first layer and the third layer and the second layer contacts a bottom of a gate dielectric.
7 . The semiconductor structure of claim 6 , wherein the first material comprises silicon dioxide (SiO2) and the second material comprises silicon nitride (SIN).
8 . The semiconductor structure of claim 6 , wherein the first layer and the third layer each comprise a first thickness and the second layer comprises a second thickness different from the first thickness.
9 . The semiconductor structure of claim 6 , wherein the first layer, the second layer, and the third layer comprise similar thicknesses.
10 . The semiconductor structure of claim 6 , wherein the first layer, the second layer, and the third layer are local isolation layers.
11 . The semiconductor structure of claim 6 comprises a uniform channel recess depth.
12 . A method, comprising:
employing a processor to facilitate execution of code instructions retained in a memory device, the processor, in response to execution of the code instructions, causes a system to perform operations comprising:
forming a semiconductor substrate;
forming a first layer comprising a first material over the semiconductor substrate;
forming a second layer over the first layer, wherein the second layer touches a bottom of a gate dielectric, the second layer comprises a second material, different from the first material;
forming a third layer over the second layer, the third layer comprises the first material;
forming a fourth layer over the third layer, wherein the fourth layer touches a bottom of an epitaxial source/drain region, the fourth layer comprises the second material, wherein the third layer is formed between the second layer and the fourth layer; and
forming a replacement metal gate.
13 . The method of claim 12 , wherein the first material comprises silicon dioxide (SiO2) and the second material comprises silicon nitride (SiN).
14 . The method of claim 12 , wherein the forming each of the first layer, the second layer, the third layer, and the fourth layer comprises forming layers that comprise a similar thickness.
15 . The method of claim 12 , further comprising forming a plurality of fins comprising performing a lithography operation and a first reactive-ion etching operation with a hard mask and four layers comprising alternative layers of tetraethyl orthosilicate (TEOS) and silicon nitride (SiN).
16 . The method of claim 15 , further comprises implementing a thermal decomposition of tetraethoxysilan (TEOS) operation, wherein a chemical-mechanical planarization operation is stopped by the silicon nitride (SiN) of the hard mask.
17 . The method of claim 16 , further comprises recessing the TEOS layer by a second reactive-ion etching operation.
18 . The method of claim 15 , further comprising:
using a second reactive-ion etching operation to strip the silicon nitrate layers of the hard mask;
performing a chemical-mechanical planarization operation on the SiN layers, wherein the chemical-mechanical planarization operation is stopped by the TEOS of the hard mask; and
recessing the SiN layers using a third reactive-ion etching operation.
19 . The method of claim 18 , further comprising stripping the TEOS of the hard mask with the third reactive-ion etching operation.
20 . The method of claim 12 , further comprising:
forming local isolation layers;
forming at least one fin using a silicon epitaxial operation; and
removing a silicon nitrite layer included in the local isolation layers.