Systems, devices, and methods for analog processing
View Patent ↗A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.
1. A quantum processor comprising:
a plurality of unit cells tiled over an area such that each unit cell is positioned adjacent at least one other unit cell, each unit cell comprising:
a first set of qubits and a second set of qubits, wherein each qubit in the first set of qubits crosses at least one qubit in the second set of qubits; and
a set of intra-cell coupling devices, wherein each intra-cell coupling device is positioned proximate a respective point where a qubit in the first set of qubits crosses a qubit in the second set of qubits and provides controllable communicative coupling between the qubit in the first set of qubits and the qubit in the second set of qubits;
and the quantum processor further comprising:
a set of inter-cell coupling devices, wherein each inter-cell coupling device in the set of inter-cell coupling devices is positioned between a respective pair of qubits in adjacent unit cells and provides controllable communicative coupling between the respective pair of qubits in adjacent unit cells.
2. The quantum processor of claim 1 wherein the quantum processor comprises a multi-layered integrated circuit.
3. The quantum processor of claim 2 wherein the quantum processor comprises a superconducting quantum processor and the multi-layered integrated circuit comprises a multi-layered superconducting integrated circuit.
4. The quantum processor of claim 3 wherein each qubit comprises a loop of superconducting material interrupted by at least one Josephson junction.
5. The quantum processor of claim 4 wherein each coupling device comprises a loop of superconducting material interrupted by at least one Josephson junction.
6. The quantum processor of claim 4 wherein each loop of superconducting material is elongated along a respective longitudinal axis and, in each unit cell:
the respective longitudinal axis of each qubit in the first set of qubits is parallel to the respective longitudinal axis of each of the other qubits in the first set of qubits and the respective longitudinal axis of each qubit in the second set of qubits is parallel to the respective longitudinal axis of each of the other qubits in the second set of qubits.
7. The quantum processor of claim 6 wherein, in each unit cell:
the respective longitudinal axis of each qubit in the first set of qubits is perpendicular to the respective longitudinal axis of each qubit in the second set of qubits such that each qubit in the first set of qubits perpendicularly crosses at least one qubit in the second set of qubits.
8. The quantum processor of claim 1 wherein, in each unit cell:
the first set of qubits includes at least four qubits and the second set of qubits includes at least four qubits, such that the unit cell includes at least eight qubits.
9. The quantum processor of claim 1 wherein each unit cell is positioned horizontally adjacent, vertically adjacent, and/or diagonally adjacent at least one other unit cell.
10. The quantum processor of claim 9 wherein each unit cell is positioned adjacent at least three other unit cells such that each unit cell is positioned horizontally adjacent at least one other unit cell, vertically adjacent at least one other cell, and diagonally adjacent at least one other cell.
11. The quantum processor of claim 1 wherein, in each unit cell:
at least a portion of each qubit in the first set of qubits is carried in a first layer and at least a portion of each qubit in the second set of qubits is carried in a second layer, such that at each respective point where a qubit in the first set of qubits crosses a qubit in the second set of qubits, the qubit in the first set of qubits and the qubit in the second set of qubits are in different layers.
12. The quantum processor of claim 11 wherein, in each unit cell:
at least a portion of each intra-cell coupling device and/or at least a portion of each inter-cell coupling device is carried in the second layer.
13. The quantum processor of claim 11 wherein, in each unit cell:
at least a portion of at each intra-cell coupling device and/or at least a portion of each inter-cell coupling device is carried in a third layer.
14. The quantum processor of claim 11 wherein, in each unit cell:
at least a portion of each qubit in the first set of qubits is carried in the second layer and/or at least a portion of each qubit in the second set of qubits is carried in the first layer.
15. The quantum processor of claim 1 wherein at least one respective pair of qubits in adjacent unit cells comprises a first qubit in the first set of qubits in a first unit cell and a second qubit in the first set of qubits in a second unit cell, wherein the second unit cell is adjacent the first unit cell, such that at least one inter-cell coupling device provides controllable communicative coupling between the first qubit in the first set of qubits in the first unit cell and the second qubit in the first set of qubits in the second unit cell.
16. The quantum processor of claim 15 wherein at least one respective pair of qubits in adjacent unit cells comprises a first qubit in the second set of qubits in a first unit cell and a second qubit in the second set of qubits in a third unit cell, wherein the third unit cell is adjacent the first unit cell, such that at least one inter-cell coupling device provides controllable communicative coupling between the first qubit in the second set of qubits in the first unit cell and the second qubit in the second set of qubits in the third unit cell.
17. The quantum processor of claim 1 wherein the respective pairs of qubits in adjacent unit cells include a first set of respective pairs of qubits in adjacent unit cells and a second set of respective pairs of qubits in adjacent unit cells, and wherein:
each respective pair of qubits in the first set of respective pairs of qubits in adjacent unit cells comprises a first qubit in the first set of qubits in one unit cell and a second qubit in the first set of qubits in an adjacent unit cell; and
each respective pair of qubits in the second set of respective pairs of qubits in adjacent unit cells comprises a first qubit in the second set of qubits in one unit cell and a second qubit in the second set of qubits in an adjacent unit cell.