IP Library Granted Patent US 9,368,576
Granted Patent B2
US 9,368,576 · App. 13/612,231 · Granted Jun 14, 2016

Methods of manufacturing trench semiconductor devices with edge termination structures

Inventors: Peilin Wang (Beijing, CN); Jingjing Chen (Beijing, CN); Edouard D. de Fresart (Tempe, AZ)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H01L29/0865H01L29/0696H01L29/4238H01L29/42372H01L29/66734H01L29/7811H01L29/7813H01L29/0869H01L29/4236
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Quick Facts
Patent No.
US 9,368,576
App. No.
13/612,231
Granted
Jun 14, 2016
Kind
B2
Abstract

Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Claims (61)

1. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

forming a gate structure in a first trench in the active region of the semiconductor substrate, wherein the gate structure has a first side and a second side, and the gate structure includes a gate electrode and a gate oxide between the gate electrode and the semiconductor substrate;

forming a termination structure in a second trench in the edge region of the semiconductor substrate, wherein the termination structure has an active region facing side and a device perimeter facing side, the second trench is partially defined by a sidewall at the active region facing side of the termination structure, and the termination structure includes an edge electrode and the gate oxide between the edge electrode and the sidewall of the second trench;

forming first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first side and the second side of the gate structure; and

forming a third source region in the semiconductor substrate adjacent to and contacting the sidewall of the second trench at the active region facing side of the termination structure.

2. The method of claim 1 , wherein providing the semiconductor substrate comprises:

providing a first semiconductor layer having the first conductivity type and defining the bottom surface, wherein the first semiconductor layer corresponds to a drain of the device; and

epitaxially forming a second semiconductor layer having the first conductivity type over the first semiconductor layer and defining the top surface, wherein the first and second trenches extend from the top surface into but not through the second semiconductor layer, and portions of the second semiconductor layer underlying the gate structure and the termination structure correspond to drift spaces of the device.

3. The method of claim 1 , further comprising:

forming a gate feed structure above the top surface in the edge region in contact with the termination structure and extending over the device perimeter facing side of the termination structure toward a perimeter of the device.

4. The method of claim 1 , wherein the termination structure substantially surrounds the active region.

5. The method of claim 1 , further comprising:

forming a body region of a second conductivity type in the semiconductor substrate between the gate structure and the termination structure, wherein the body region extends from the first side of the gate structure to the active region facing side of the termination structure, and wherein the first and third source regions are formed in the body region.

6. The method of claim 1 , further comprising:

forming at least one additional gate structure in at least one additional trench in parallel with the first trench; and

forming additional source regions in the semiconductor substrate adjacent both sides of the at least one additional gate structure.

7. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

forming a gate structure in a first trench in the active region of the semiconductor substrate, wherein the gate structure has a first side and a second side;

forming a termination structure in a second trench in the edge region of the semiconductor substrate, wherein the termination structure has an active region facing side and a device perimeter facing side, and wherein the termination structure substantially surrounds the active region;

forming first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first side and the second side of the gate structure; and

forming a third source region in the semiconductor substrate adjacent the active region facing side of the termination structure;

forming an extension electrode in a third trench in the edge region, wherein the extension electrode extends from the device perimeter facing side of the termination structure; and

forming a gate feed structure above the top surface in the edge region in contact with an end of the extension electrode and extending toward a perimeter of the device.

8. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

forming a gate structure in a first trench in the active region of the semiconductor substrate, wherein the gate structure has a first side and a second side, and the gate structure includes a gate electrode and a gate oxide between the gate electrode and the semiconductor substrate;

forming a termination structure in a second trench in the edge region of the semiconductor substrate, wherein the termination structure has an active region facing side and a device perimeter facing side, the second trench is partially defined by a sidewall at the active region facing side of the termination structure, and the termination structure includes an edge electrode and the gate oxide between the edge electrode and the sidewall of the second trench;

forming a body region of a second conductivity type in the semiconductor substrate between the gate structure and the termination structure, wherein the body region extends from the first side of the gate structure to the active region facing side of the termination structure;

forming an enhanced body region of the second conductivity type and a higher doping density in the body region;

forming first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first side and the second side of the gate structure, wherein the first source region is formed in the body region; and

forming a third source region in the semiconductor substrate adjacent to and contacting the sidewall of the second trench at the active region facing side of the termination structure, wherein the third source region is formed in the body region.

9. A method for forming a trench metal oxide semiconductor device, comprising:

providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

forming a plurality of parallel gate structures in a plurality of parallel first trenches in the active region of the semiconductor substrate, wherein each of the gate structures has a first side and a second side, and each of the gate structures includes a gate electrode and a gate oxide between the gate electrode and the semiconductor substrate;

forming a termination structure in a second trench in the edge region of the semiconductor substrate, wherein the termination structure has an active region facing side and a device perimeter facing side, the second trench is partially defined by a sidewall at the active region facing side of the termination structure, and the termination structure includes an edge electrode and the gate oxide between the edge electrode and the sidewall of the second trench;

forming first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first sides and the second sides of the gate structures; and

forming a third source region in the semiconductor substrate adjacent to and contacting the sidewall of the second trench at the active region facing side of the termination structure.

10. The method of claim 9 , further comprising:

forming a gate feed structure above the top surface in the edge region in contact with the termination structure and extending over the device perimeter facing side of the termination structure toward a perimeter of the device.

11. The method of claim 9 , wherein forming the termination structure comprises:

forming the second trench in the edge region to substantially surround the active region; and

forming the termination structure in the second trench.

12. A method for forming a trench metal oxide semiconductor device, wherein the device has a first side, a second side, a third side, and a fourth side, and the method comprises:

providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

forming a plurality of parallel gate structures in a plurality of parallel first trenches in the active region of the semiconductor substrate, wherein each of the gate structures has a first side and a second side;

forming a second trench in the edge region to substantially surround the active region, wherein forming the second trench comprises:

forming the second trench to include four trench segments in the edge region, wherein a first trench segment is proximate to and parallel with the first side of the device and is parallel with the gate structures, a second trench segment is proximate to and parallel with the second side of the device and is perpendicular to the first trench segment and the gate structures, a third trench segment is proximate to and parallel with the third side of the device and is parallel with the first trench segment and the gate structures and perpendicular to the second trench segment, and a fourth trench segment is proximate to and parallel with the fourth side of the device and is parallel with the second trench segment and perpendicular to the first and third trench segments and the gate structures;

forming a termination structure in the second trench, wherein the termination structure has an active region facing side and a device perimeter facing side;

forming first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first sides and the second sides of the gate structures; and

forming a third source region in the semiconductor substrate adjacent the active region facing side of the termination structure.

13. The method of claim 12 , further comprising:

forming an extension electrode in a third trench in the edge region, wherein the extension electrode extends from the device perimeter facing side of the second trench segment; and

forming a gate feed structure above the top surface in the edge region in contact with an end of the extension electrode and extending toward a perimeter of the device.

14. The method of claim 13 , wherein the second trench segment has a zig-zag configuration that includes of a series of straight, parallel trench walls that intersect at angles.

15. The method of claim 13 , wherein the second trench segment has a zig-zag configuration that includes of a series of curved parallel trench walls that intersect smoothly at turning points.

16. The method of claim 13 , wherein the extension electrode extends at substantially a right angle from the device perimeter facing side of the second trench segment.

17. The method of claim 13 , further comprising:

forming a plurality of additional extension electrodes in additional trenches in the edge region, wherein the additional extension electrodes extend from the device perimeter facing side of the second trench segment, and

wherein the gate feed structure contacts ends of the additional extension electrodes.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2012
From: WANG, PEILIN; CHEN, JINGJING; DE FRESART, EDOUARD D.
To: FREESCALE SEMICONDUCTOR, INC.
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Priority Claims (1)
CN 2012 1 0291502 · May 17, 2012 · national
Continuity (1)
Related Publication 20130307060A1 · Nov 21, 2013