Semiconductor memory device and methods of operating the same

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory blocks each comprising a plurality of pages, wherein each of the plurality of pages comprises at least one flag cell indicating whether data is stored in a corresponding page; and

a peripheral circuit configured to read data from the flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells,

wherein when a program operation is performed on each of the plurality of pages before the erase request is received, a corresponding flag cell is programmed to have a program state,

wherein the peripheral circuit is configured to perform the erase operation when at least one of the flag cells of the selected memory block is in the program state and to omit the erase operation when the flag cells of the selected memory block are in an erase state.

2. The semiconductor memory device of claim 1 , wherein the peripheral circuit is configured to supply an identical voltage to word lines coupled to the flag cells of the selected memory block when a bit line coupled to the flag cells of the selected memory block is precharged, and then wherein the peripheral circuit is configured to sense a voltage of the bit line to determine whether at least one of the flag cells of the selected memory block is in the program state or the flag cells of the selected memory block are in the erase state.

3. The semiconductor memory device of claim 1 , wherein data of the flag cells is erased when an erase operation is performed on the selected memory block.

4. The semiconductor memory device of claim 1 , wherein:

the plurality of pages comprises a plurality of even pages and a plurality of odd pages, and

the plurality of pages further comprises first flag cells indicating whether data is stored in the plurality of even pages, and second flag cells indicating whether data is stored in the plurality of odd pages.

5. The semiconductor memory device of claim 4 , wherein the peripheral circuit is configured to read data from the first flag cells of the selected memory block and data from the second flag cells of the selected memory block and to omit the erase operation based on the read data.

6. A method of erasing a semiconductor memory device, the method comprising:

programming a flag cell included in a page of a selected memory block to have a program state when a program operation is performed on the page before an erase request is received;

reading data from flag cells in pages of the selected memory block in response to the erase request; and

omitting an erase operation on the selected memory block when the flag cells in the pages of the selected memory block are in an erase state; and

performing the erase operation when at least one of the flag cells of the selected memory block is in the program state.