Stacked semiconductor package

1. A stacked semiconductor package comprising:

a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and

interconnections electrically connecting the repair pads of the semiconductor chips; and

conductive connection members formed between the through-silicon vias of the stacked semiconductor chips; and

adhesive members formed between the stacked semiconductor chips.

2. The stacked semiconductor package according to claim 1 , wherein the through-silicon vias of any one upper semiconductor chip among the plurality of stacked semiconductor chips and at least any one of the through-silicon vias of a semiconductor chip placed immediately below the upper semiconductor chip are not electrically connected with each other.

3. The stacked semiconductor package according to claim 1 , wherein the interconnections are formed on the side surfaces of the stacked semiconductor chips.

4. The stacked semiconductor package according to claim 3 , further comprising:

a molding part sealing an upper surface of the stacked semiconductor chips and the side surfaces of the stacked semiconductor chips including the interconnections.

5. The stacked semiconductor package according to claim 4 , further comprising:

first additional interconnections formed in the molding part, and having one ends which are electrically connected with the interconnections and other ends which face away from the one ends and are exposed out of the molding part.

6. The stacked semiconductor package according to claim 5 , further comprising:

second additional interconnections formed on the molding part and electrically connecting the other ends of the first additional interconnections which are exposed out of the molding part.

7. The stacked semiconductor package according to claim 1 , further comprising:

a molding part covering an upper surface and side surfaces of the stacked semiconductor chips.

8. The stacked semiconductor package according to claim 7 , wherein the interconnections comprise:

first interconnections formed in the molding part and having one ends which are electrically connected with the repair pads of the respective semiconductor chips and other ends which face away from the one ends and are exposed out of the molding part; and

second interconnections formed on the molding part and electrically connecting the other ends of the first interconnections which are exposed out of the molding part.

9. The stacked semiconductor package according to claim 1 , wherein the interconnections are electrically connected with the repair pads of some semiconductor chips among the stacked semiconductor chips.

10. The stacked semiconductor package according to claim 1 , wherein the interconnections are electrically connected with the repair pads of all the stacked semiconductor chips.

11. The stacked semiconductor package according to claim 1 , wherein the repair pads are formed to be exposed on the side surfaces of the substrate on edges of the one surface of the substrate, and the wiring lines are formed on the one surface of the substrate.

12. The stacked semiconductor package according to claim 11 , wherein each of the semiconductor chips further includes a protective layer which is formed on the one surface of the substrate in such a way as to cover the wiring lines and leave exposed the repair pads and the through-silicon vias.

13. The stacked semiconductor package according to claim 1 , wherein the repair pads are formed on the side surfaces of the substrate, and the wiring lines are formed in the substrate.

14. The stacked semiconductor package according to claim 1 , further comprising:

a first dielectric layer formed under a lower surface of a lowermost semiconductor chip among the stacked semiconductor chips in such a way as to expose the through-silicon vias of the lowermost semiconductor chip;

redistribution lines formed under the first dielectric layer and electrically connected with the through-silicon vias of the lowermost semiconductor chip; and

a second dielectric layer formed under the first dielectric layer including the redistribution lines in such a way as to expose portions of the redistribution lines.

15. The stacked semiconductor package according to claim 14 , further comprising:

external connection terminals mounted to the portions of the redistribution lines exposed through the second dielectric layer.

16. The stacked semiconductor package according to claim 1 , further comprising:

a structural body supporting the semiconductor chips and having connection electrodes which are electrically connected with the through-silicon vias of the lowermost semiconductor chip among the stacked semiconductor chips.

17. The stacked semiconductor package according to claim 16 , wherein the structural body comprises any one of a printed circuit board, an interposer and a semiconductor package.