Secure key self-generation
View Patent ↗Techniques are disclosed for providing secure critical security parameter (CSP) generation in an integrated circuit (IC). Embodiments generally include determining that an ability to read the CSP externally (e.g., through a debug interface) has been disabled before the CSP is generated. Depending on the functionality of the device, embodiments can include other steps, such as determining whether software for executing a method for providing a secure CSP is being run for a first time. Among other things, the techniques provided herein for providing secure CSP generation can increase the security of the CSP and reduce manufacturing costs of the IC.
1. A computer-implemented method for providing secure critical security parameter (CSP) generation for an integrated circuit, the method comprising:
determining that an interface operable to provide access to a secure memory of the integrated circuit is disabled;
detecting that a first CSP is stored in a memory of the integrated circuit, wherein detecting that the first CSP is stored in the memory is done in response to determining that the interface is disabled;
determining that the computer-implemented method is being executed by the integrated circuit for a first time; and
performing the following operations in response to determining that the method is being executed by the integrated circuit for a first time:
erasing the first CSP from the memory;
generating a second CSP; and
storing the second CSP in the secure memory of the integrated circuit.
2. The computer-implemented method for providing CSP generation for an integrated circuit as recited in claim 1 , further comprising protecting the second CSP from being erased from the secure memory of the integrated circuit.
3. The computer-implemented method for providing CSP generation for an integrated circuit as recited in claim 1 , further comprising:
determining that the interface is not disabled subsequent to a reboot of the integrated circuit; and
preventing normal operation of the integrated circuit.
4. The computer-implemented method for providing CSP generation for an integrated circuit as recited in claim 3 , wherein the normal operation of the integrated circuit is prevented by putting the integrated circuit into an error or halt state.
5. The computer-implemented method for providing CSP generation for an integrated circuit as recited in claim 1 , wherein the interface of the integrated circuit is a debugging interface.
6. The computer-implemented method for providing CSP generation for an integrated circuit as recited in claim 1 , wherein the second CSP comprises a public/private pair of encryption keys.
7. The computer-implemented method for providing CSP generation for an integrated circuit as recited in claim 1 , wherein the second CSP is generated by the integrated circuit.
8. The computer-implemented method for providing CSP generation for an integrated circuit as recited in claim 1 , further comprising rebooting the integrated circuit after storing the second CSP in the secure memory of the integrated circuit.
9. A non-transitory computer-readable medium having instructions embedded thereon for providing secure critical security parameter (CSP) generation for an integrated circuit, the instructions including computer-executable code for:
determining that an interface operable to provide access to a secure memory of the integrated circuit is disabled;
detecting that a first CSP is stored in a memory of the integrated circuit, wherein detecting that the first CSP is stored in the memory is done in response to determining that the interface is disabled;
determining that the computer-executable code is being executed by the integrated circuit for a first time;
performing the following operations in response to determining that the computer-executable code is being executed by the integrated circuit for a first time:
erasing the first CSP from the memory;
generating a second CSP; and
storing the second CSP in the secure memory of the integrated circuit.
10. The non-transitory computer-readable medium recited in claim 9 , further comprising computer-executable code for protecting the second CSP from being erased from the secure memory of the integrated circuit.
11. The non-transitory computer-readable medium recited in claim 9 , further comprising computer-executable code for:
determining that the interface is not disabled subsequent to a reboot of the integrated circuit; and
preventing normal operation of the integrated circuit.
12. The non-transitory computer-readable medium recited in claim 11 , wherein the computer-executable code for preventing the normal operation of the integrated circuit includes computer-executable code for putting the integrated circuit into an error or halt state.
13. The non-transitory computer-readable medium recited in claim 9 , wherein the interface of the integrated circuit is a debugging interface.
14. The non-transitory computer-readable medium recited in claim 9 , wherein the second CSP comprises a public/private pair of encryption keys.
15. An integrated circuit capable of securely generating a critical security parameter (CSP), the integrated circuit comprising:
a secure memory;
an interface; and
processing circuitry, coupled to the secure memory and the interface, and configured to execute a process, wherein the process comprises:
determining that an interface operable to provide access to a secure memory of the integrated circuit is disabled;
detecting that a first CSP is stored in a memory of the integrated circuit, wherein detecting that the first CSP is stored in the memory is done is response to determining that the interface is disabled;
determining that the initial process is being executed by the processing circuitry for a first time;
performing the following operations in response to determining that the process is being executed by the processing circuitry for a first time:
erasing the first CSP from the memory;
generating a second CSP; and
storing the second CSP in the secure memory of the integrated circuit.
16. The integrated circuit capable of providing CSP generation as recited in claim 15 , wherein the processing circuitry is configured to protect the second CSP from being erased from the secure memory.
17. The integrated circuit capable of providing CSP generation as recited in claim 15 , wherein the process further comprises:
determining that the interface is not disabled subsequent to a reboot of the integrated circuit; and
preventing normal operation of the integrated circuit.
18. The integrated circuit capable of providing CSP generation as recited in claim 17 , wherein the normal operation of the integrated circuit is prevented by putting the integrated circuit into an error or halt state.
19. The integrated circuit capable of providing CSP generation as recited in claim 17 , wherein the interface is a debugging interface.
20. The integrated circuit capable of providing CSP generation as recited in claim 15 , wherein the second CSP comprises a public/private pair of encryption keys.