Memory modules with reliability and serviceability functions
View Patent ↗One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.
1. A memory module comprising:
a plurality of memory chips comprising a first memory chip and a second memory chip;
a plurality of intelligent buffer chips comprising:
a first intelligent buffer chip coupled to the first memory chip, wherein the first intelligent buffer chip includes a first temperature monitoring device configured to perform temperature measurements of the first memory chip; and
a distinct second intelligent buffer chip coupled to the second memory chip, wherein the second intelligent buffer chip includes a second temperature monitoring device configured to perform temperature measurements of the second memory chip;
an intelligent register chip coupled to a memory controller; and
a sideband bus coupling the intelligent register chip and the plurality of intelligent buffer chips,
wherein the intelligent register chip is configured to receive (i) from the first intelligent buffer chip via the sideband bus, first data representing the temperature measurements of the first memory chip and (ii) from the second intelligent buffer chip via the sideband bus, second data representing the temperature measurements of the second memory chip.
2. The memory module of claim 1 , further comprising:
a serial presence detect (SPD) chip coupled to the memory controller and the intelligent register chip, the SPD chip configured to:
receive the first data and the second data from the intelligent register chip;
store the first data and the second data; and
provide the first data and the second data to the memory controller.
3. The memory module of claim 1 , wherein the first intelligent buffer chip and the first memory chip form a first stack on the memory module, and the second intelligent buffer chip and the second memory chip form a second stack on the memory module.
4. The memory module of claim 1 , wherein the intelligent register chip is configured to issue commands via the sideband bus to reduce power consumption of the first intelligent buffer chip.
5. The memory module of claim 4 , wherein the intelligent register chip is configured to turn off an output buffer of the first intelligent buffer chip.
6. The memory module of claim 1 , wherein the first intelligent buffer chip is configured to control a light-emitting diode to indicate a failure of the memory module.
7. The memory module of claim 1 , wherein the intelligent register chip is configured to perform a self-test on the memory module.
8. A memory module comprising:
a plurality of memory chips comprising a first memory chip and a second memory chip;
a plurality of intelligent buffer chips comprising:
a first intelligent buffer chip coupled to the first memory chip, wherein the first intelligent buffer chip includes a first temperature monitoring device configured to perform temperature measurements of the first memory chip; and
a distinct second intelligent buffer chip coupled to the second memory chip, wherein the second intelligent buffer chip includes a second temperature monitoring device configured to perform temperature measurements of the second memory chip;
an intelligent register chip coupled to a memory controller;
a sideband bus coupling the intelligent register chip and the plurality of intelligent buffer chips;
a first data bus coupling the intelligent register chip and the first memory chip; and
a second data bus coupling the intelligent register chip and the second memory chip,
wherein the intelligent register chip is configured to receive (i) from the first intelligent buffer chip via the sideband bus, first data representing the temperature measurements of the first memory chip and (ii) from the second intelligent buffer chip via the sideband bus, second data representing the temperature measurements of the second memory chip.
9. The memory module of claim 8 , further comprising:
a serial presence detect (SPD) chip coupled to the memory controller and the intelligent register chip, the SPD chip configured to:
receive the first data and the second data from the intelligent register chip;
store the first data and the second data; and
provide the first data and the second data to the memory controller.
10. The memory module of claim 8 , wherein the first intelligent buffer chip and the first memory chip form a first stack on the memory module, and the second intelligent buffer chip and the second memory chip form a second stack on the memory module.
11. The memory module of claim 8 , wherein the intelligent register chip is configured to issue commands via the sideband bus to reduce power consumption of the first intelligent buffer chip.
12. The memory module of claim 11 , wherein the intelligent register chip is configured to turn off an output buffer of the first intelligent buffer chip.
13. The memory module of claim 8 , wherein the first intelligent buffer chip is configured to control a light-emitting diode to indicate a failure of the memory module.
14. The memory module of claim 8 , wherein the intelligent register chip is configured to perform a self-test on the memory module.
15. A memory module comprising:
a plurality of memory chips comprising a first memory chip and a second memory chip;
a plurality of intelligent buffer chips comprising:
a first intelligent buffer chip coupled to the first memory chip, wherein the first intelligent buffer chip includes a first temperature monitoring device configured to perform temperature measurements of the first memory chip; and
a distinct second intelligent buffer chip coupled to the second memory chip, wherein the second intelligent buffer chip includes a second temperature monitoring device configured to perform temperature measurements of the second memory chip;
an intelligent register chip coupled to a memory controller;
a sideband bus coupling the intelligent register chip and the plurality of intelligent buffer chips;
a first data bus coupling the memory controller and the first memory chip; and
a second data bus coupling the memory controller and the second memory chip,
wherein the intelligent register chip is configured to receive (i) from the first intelligent buffer chip via the sideband bus, first data representing the temperature measurements of the first memory chip and (ii) from the second intelligent buffer chip via the sideband bus, second data representing the temperature measurements of the second memory chip.
16. The memory module of claim 15 , further comprising:
a serial presence detect (SPD) chip coupled to the memory controller and the intelligent register chip, the SPD chip configured to:
receive the first data and the second data from the intelligent register chip;
store the first data and the second data; and
provide the first data and the second data to the memory controller.
17. The memory module of claim 15 , wherein the first intelligent buffer chip and the first memory chip form a first stack on the memory module, and the second intelligent buffer chip and the second memory chip form a second stack on the memory module.
18. The memory module of claim 15 , wherein the intelligent register chip is configured to issue commands via the sideband bus to reduce power consumption of the first intelligent buffer chip.
19. The memory module of claim 18 , wherein the intelligent register chip is configured to turn off an output buffer of the first intelligent buffer chip.
20. The memory module of claim 15 , wherein the first intelligent buffer chip is configured to control a light-emitting diode to indicate a failure of the memory module.