IP Library Granted Patent US 9,110,783
Granted Patent B1
US 9,110,783 · App. 13/618,851 · Granted Aug 18, 2015

Application-transparent hybridized caching for high-performance storage

Inventors: Kushagra Vaid (Sammamish, WA); Sompong Paul Olarig (Pleasanton, CA)
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
G06F12/0246G11C16/102
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Quick Facts
Patent No.
US 9,110,783
App. No.
13/618,851
Granted
Aug 18, 2015
Kind
B1
Abstract

Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.

Claims (19)

1. A method for hybridizing cache memory having at least one magnetic media and at least one solid-state media, the method comprising:

receiving a read request to retrieve a data block;

checking whether the at least one solid-state media is available to fulfill the read request;

when the at least one solid-state media is able to fulfill the read request, completing the read request without utilizing the magnetic media; and

when the at least one solid-state media is unable to fulfill the read request, substantially simultaneously performing both of the following:

(1) completing the read request at the at least one magnetic media; and

(2) updating the solid-state media with the data block retrieved from the at least one magnetic media.

2. The method of claim 1 , wherein the at least one solid-state media is a non-volatile memory.

3. The method of claim 1 , wherein the request includes at least a LBA number and an operand size that denotes the size of a data block request.

4. The method of claim 1 , wherein a data block is returned by a disk array controller in response to the read request.

5. One or more hardware computer-storage media devices having computer-executable instructions embodied thereon that, when executed by a computing device, perform a method for hybridizing cache memory of a serving computer system, the method comprising:

receiving, at a Redundant Array of Inexpensive Disks (RAID) storage controller in communication with at least a solid state cache control logic component and an associative memory component, a request for a hosted computing operation to retrieve a data block;

consulting a memory array associated with a cache memory component, by the storage controller, to determine if a cache hit or cache miss occurred:

when a cache hit occurs, determining, by a solid-state cache memory controller, if the request is for a hosted-read operation or a hosted-write operation, wherein if the request is a hosted-read operation, retrieving the data block from a solid-state cache memory component; and

when a cache miss occurs, determining, by the solid-state cache memory controller, if the request is for a hosted-read operation or a hosted-write operation, wherein if the request is a hosted-read operation, retrieving the data block from a magnetic-disk memory component, and completing the hosted-read operation request and copying the data block to the solid-state cache memory component on a first read access operation.

6. The media of claim 5 , wherein the solid-state cache memory component is located remotely from the solid-state cache control component.

7. The media of claim 5 , wherein the solid-state cache memory component is a non-volatile memory.

8. The media of claim 5 , wherein one or more additional solid-state cache memory components can be added without disruption to the host computing system.

9. The media of claim 5 , wherein the solid-state cache controller is one of an external controller communicating with the storage controller, an embedded component within the storage controller, or a controller within a plurality of controllers manipulated by a centralized controller.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2015
From: MICROSOFT CORPORATION
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 039025/0454 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2012
From: VAID, KUSHAGRA; OLARIG, SOMPONG PAUL
To: MICROSOFT CORPORATION
Reel/Frame 029201/0662 →
Continuity (2)
Continuation 12695552 · Jan 28, 2010
Provisional Application 61632416 · Jun 15, 2009