Shared memory multi video channel display apparatus and methods
View Patent ↗A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.
1. A video processing system comprising:
a first plurality of line buffers configured to provide a first set of buffered field lines from an input video field;
a second plurality of line buffers configured to provide a second set of buffered field lines from a twice-delayed noise reduced video field; and
a noise reducer configured to:
receive field lines of the input video field, field lines of the twice-delayed noise reduced video field, the first set of buffered field lines, and the second set of buffered field lines; and
output a noise reduced video field.
2. The video processing system of claim 1 further comprising:
a first field buffer configured to receive the noise reduced video field and to provide a once-delayed noise reduced video field; and
a second field buffer configured to receive the once-delayed noise reduced video field and to provide the twice-delayed noise reduced video field.
3. The video processing system of claim 2 , wherein the first plurality of line buffers comprises:
a first line buffer configured to receive a field line of the input video field and to provide a first buffered field line; and
a second line buffer configured to receive the first buffered field line and to provide a second buffered field line;
wherein the first set of buffered field lines comprises the first buffered field line and the second buffered field line.
4. The video processing system of claim 3 , wherein the second plurality of line buffers comprises:
a third line buffer configured to receive a field line of the twice-delayed noise reduced video field and to provide a third buffered field line; and
a fourth line buffer configured to receive the third buffered field line and to provide a fourth buffered field line;
wherein the second set of buffered field lines comprises the third buffered field line and the fourth buffered field line.
5. The video processing system of claim 2 further comprising:
a deinterlacer configured to:
receive field lines of the input video field, field lines of the once-delayed noise reduced video field, and the second set of buffered field lines; and
output a de-interlaced video signal.
6. The video processing system of claim 2 further comprising:
a deinterlacer configured to:
receive field lines of the noise reduced video field, field lines of the once-delayed noise reduced video field, and the second set of buffered field lines; and
output a de-interlaced video signal.
7. The video processing system of claim 6 further comprising:
a third plurality of line buffers configured to provide a third set of buffered field lines from the noise reduced video field; and
a fourth plurality of line buffers configured to provide a fourth set of buffered field lines from the once-delayed noise reduced video field;
wherein the deinterlacer is further configured to receive the third set of buffered field lines and the fourth set of buffered field lines.
8. The video processing system of claim 7 , wherein the first set of buffered field lines comprises at least two buffered field lines, the second set of buffered field lines comprises at least three buffered field lines, the third set of buffered field lines comprises at least two buffered field lines, and the fourth set of buffered field lines comprises at least three buffered field lines.
9. The video processing system of claim 6 , wherein the noise reducer and deinterlacer are configured to share the second plurality of line buffers.
10. A method of operating a video processing system, the method comprising:
processing field lines of an input video field, field lines of a twice-delayed noise reduced video field, a first set of buffered field lines, and a second set of buffered field lines to produce a noise reduced video field;
wherein the first set of buffered field lines comprises buffered field lines from the input video field; and
wherein the second set of buffered field lines comprises buffered field lines from the twice-delayed noise reduced video field.
11. The method of claim 10 further comprising:
storing the noise reduced video field in a first field buffer;
moving a once-delayed noise reduced video field from the first field buffer to the second field buffer; and
receiving the twice-delayed noise reduced video field from the second field buffer.
12. The method of claim 11 further comprising:
storing a field line of the input video field in a first line buffer; and
moving a previously buffered field line from the first line buffer to a second line buffer.
13. The method of claim 12 further comprising:
storing a field line of the twice-delayed noise reduced video field in a third line buffer; and
moving a previously buffered field line from the third line buffer to a fourth line buffer.
14. The method of claim 11 further comprising:
processing field lines of the input video field, field lines of the once-delayed noise reduced video field, and the second set of buffered field lines to produce a de-interlaced video signal.
15. The method of claim 11 further comprising:
processing field lines of the noise reduced video field, field lines of the once-delayed noise reduced video field, and the second set of buffered field lines to produce a de-interlaced video signal.
16. The method of claim 11 further comprising:
processing field lines of the noise reduced video field, field lines of the once-delayed noise reduced video field, the second set of buffered field lines, a third set of buffered field lines, and a fourth set of buffered field lines to produce a de-interlaced video signal;
wherein the third set of buffered field lines comprises buffered field lines from the noise reduced video field; and
wherein the fourth set of buffered field lines comprises buffered field lines from the once-delayed noise reduced video field.
17. The method of claim 16 , wherein the first set of buffered field lines comprises at least two buffered field lines, the second set of buffered field lines comprises at least three buffered field lines, the third set of buffered field lines comprises at least two buffered field lines, and the fourth set of buffered field lines comprises at least three buffered field lines.
18. The method of claim 16 , wherein the noise reduced video field is produced by a noise reducer and the de-interlaced video signal is produced by a de-interlacer.
19. The method of claim 18 , wherein the first set of buffered field lines are stored in a first plurality of line buffers, the second set of buffered field lines are stored in a second plurality of line buffers, the third set of buffered field lines are stored in a third plurality of line buffers, and the fourth set of buffered field lines are stored in a fourth plurality of line buffers.
20. The method of claim 19 , wherein the noise reducer and deinterlacer are configured to share the second plurality of line buffers.