Controller for one type of NAND flash memory for emulating another type of NAND flash memory

1. A method of reading host data from a flash memory device, the method comprising:

a) receiving from a host device a read instruction to read host data from an array of NAND flash memory cells grouped into separately-readable device pages, the host data being a portion of device data that is stored in a device page;

b) parsing the host data from device data; and

c) sending the parsed host data to the host device;

wherein receiving the read instruction includes receiving a host command sequence and parsing the host command sequence;

wherein the host command sequence is a Single Bit per Cell command sequence; and

wherein the host command sequence is parsed into a device command sequence to handle the host data in compliance with a Multi Bit per Cell operation.

2. The method according to claim 1 ,

wherein the receiving, parsing, and sending are performed by a controller of the flash memory device.

3. The method according to claim 1 ,

wherein the host command sequence is parsed into a host opcode defining the read instruction and a host logical address associated with the host data.

4. The method according to claim 3 , wherein parsing the host data from device data includes translating a host logical address associated with the host data into a corresponding physical address of a device block that contains the host data.

5. The method according to claim 4 , wherein translating the host logical address includes consulting a translation table for the address of the device block that stores the device data that includes the host data to be parsed.

6. The method according to claim 1 ,

wherein the host device is a Single Bit per Cell device; and

wherein the flash memory device is a Multi Bit per Cell device.

7. The method according to claim 6 ,

wherein the host data is defined by Single Bit per Cell data;

wherein the device data is defined by Multi Bit per Cell data; and

wherein the Single Bit per Cell data is a portion of the Multi Bit per Cell data.

8. A controller for a flash memory device, the controller comprising:

a) a host NAND interface adapted to receive from a host device a read instruction to read host data from an array of NAND flash memory cells grouped into separately-readable device pages, the host data being a portion of device data that is stored in a device page; and

b) control circuitry adapted to parse the host data from device data and send the parsed host data to the host device;

a host command parser for parsing a host command sequence that defines the read instruction;

wherein the host command sequence is a Single Bit per Cell command sequence; and

wherein the host command parser parses the host command sequence into a device command sequence to handle the host data in compliance with a Multi Bit per Cell operation.

9. The controller according to claim 8 ,

wherein the host command parser parses the host command sequence into a host opcode defining the read instruction and a host logical address associated with the host data.

10. The controller according to claim 9 , wherein the control circuitry is adapted to parse the host data from device data by translating a host logical address associated with the host data into a corresponding physical address of a device block that contains the host data.

11. The controller according to claim 10 , wherein translating the host logical address includes consulting a translation table for the address of the device block that stores the device data that includes the host data to be parsed.

12. The controller according to claim 8 ,

wherein the host device is a Single Bit per Cell device; and

wherein the flash memory device is a Multi Bit per Cell device.

13. The controller according to claim 12 ,

wherein the host data is defined by Single Bit per Cell data;

wherein the device data is defined by Multi Bit per Cell data; and

wherein the Single Bit per Cell data is a portion of the Multi Bit per Cell data.

14. A memory device having logic for executing a read instruction to read host data from the memory device, the logic configured to perform the following operations:

a) receiving from a host device a read instruction to read host data from an array of NAND flash memory cells grouped into separately-readable device pages, the host data being a portion of device data that is stored in a device page, wherein receiving the read instruction includes receiving a host command sequence and parsing the host command sequence, wherein the host command sequence is a Single Bit per Cell command sequence, and wherein the host command sequence is parsed into a device command sequence to handle the host data in compliance with a Multi Bit per Cell operation;

b) parsing the host data from device data; and

c) sending the parsed host data to the host device.

15. The memory device according to claim 14 ,

wherein the host command sequence is parsed into a host opcode defining the read instruction and a host logical address associated with the host data.

16. The memory device according to claim 15 , wherein parsing the host data from device data includes translating a host logical address associated with the host data into a corresponding physical address of a device block that contains the host data.

17. The memory device according to claim 16 , wherein translating the host logical address includes consulting a translation table for the address of the device block that stores the device data that includes the host data to be parsed.

18. The memory device according to claim 14 ,

wherein the host device is a Single Bit per Cell device; and

wherein the flash memory device is a Multi Bit per Cell device.

19. The memory device according to claim 18 ,

wherein the host data is defined by Single Bit per Cell data;

wherein the device data is defined by Multi Bit per Cell data; and

wherein the Single Bit per Cell data is a portion of the Multi Bit per Cell data.