Power management of memory circuits by virtual memory simulation
View Patent ↗An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
1. An apparatus comprising:
a plurality of physical memory circuits; and
an interface circuit configured to:
communicate between the plurality of physical memory circuits and a memory controller;
simulate one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits;
receive, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and
issue one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits.
2. The apparatus of claim 1 , wherein the first address timing includes a 1T address timing and the second address timing includes a 2T address timing, and wherein the interface circuit is configured to change the address timing of the one or more virtual memory circuits from the 1T address timing to the 2T address timing to increase the precharge-to-active ratio of the one or more virtual memory circuits.
3. The apparatus of claim 1 , wherein the address timing of the one or more virtual memory circuits includes a minimum clock cycle timing between a first command and a subsequent command received by the interface circuit, and wherein a change in the minimum clock cycle timing changes the precharge-to-active ratio of the one or more virtual memory circuits.
4. The apparatus of claim 1 , wherein the interface circuit is configured to determine the change in the address timing associated with the one or more virtual memory circuits so as to increases a likelihood of at least one of the physical memory circuits entering a precharge mode to increase the precharge-to-active ratio of the one or more virtual memory circuits.
5. The apparatus of claim 1 , wherein the interface circuit is configured to receive a command to dynamically change from the first address timing to the second address timing associated with the one or more virtual memory circuits.
6. The apparatus of claim 5 , wherein the address timing of the one or more virtual memory circuits is dynamically changed based on at least one of a past command, a present command, or an anticipated command from the memory controller to the one or more virtual memory circuits.
7. A method comprising:
communicating, by an interface circuit, between a plurality of physical memory circuits and a memory controller;
simulating, by the interface circuit, one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits;
receiving, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and
issuing, by the interface circuit, one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits.
8. The method of claim 7 , wherein the first address timing includes a 1T address timing and the second address timing includes a 2T address timing, and wherein a change from the 1T address timing to the 2T address timing increases the precharge-to-active ratio of the one or more virtual memory circuits.
9. The method of claim 7 , wherein the address timing of the one or more virtual memory circuits includes a minimum clock cycle timing between a first command and a subsequent command received by the interface circuit, and wherein a change in the minimum clock cycle timing changes the precharge-to-active ratio of the one or more virtual memory circuits.
10. The method of claim 7 , comprising:
receiving a command to dynamically change from the first address timing to the second address timing associated with the one or more virtual memory circuits.
11. An apparatus comprising:
a memory controller; and
a memory module comprising:
a plurality of physical memory circuits; and
an interface circuit configured to:
communicate between the plurality of physical memory circuits and the memory controller;
simulate one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits;
receive, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and
issue one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits.
12. The apparatus of claim 11 , wherein the first address timing includes a 1T address timing and the second address timing includes a 2T address timing, and wherein the interface circuit is configured to change the address timing of the one or more virtual memory circuits from the 1T address timing to the 2T address timing to increase the precharge-to-active ratio of the one or more virtual memory circuits.
13. The apparatus of claim 11 , wherein the address timing of the one or more virtual memory circuits includes a minimum clock cycle timing between a first command and a subsequent command received by the interface circuit, and wherein a change in the minimum clock cycle timing changes the precharge-to-active ratio of the one or more virtual memory circuits.
14. The apparatus of claim 11 , wherein the interface circuit is configured to receive a command to dynamically change from the first address timing to the second address timing associated with the one or more virtual memory circuits.