Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
View Patent ↗A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.
1. A controller, comprising:
a first external terminal configured to correspond to a system clock to which a semiconductor memory device receives, the system clock having a first frequency or a second frequency;
a second external terminal configured to supply a command to the semiconductor memory device;
a third external terminal configured to communicate a data with the semiconductor memory device;
a fourth external terminal configured to transmit a data strobe signal having a preamble and a toggle transition following to the preamble, the preamble corresponding to a start timing of communicating the data and the toggle transition corresponding to communicating the data between the controller and the semiconductor memory device; and
a fifth external terminal configured to be capable of outputting an information specifying a length of the preamble to the semiconductor memory device, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.
2. The controller as claimed in claim 1 , the controller further comprising:
a preamble length determination unit configured to determine the length of the preamble.
3. The controller as claimed in claim 2 ,
wherein the preamble length determination unit determines the length of the preamble based on a frequency of the system clock.
4. The controller as claimed in claim 1 ,
wherein the length is one of 1CK of the system clock and 2CK of the system clock.
5. The controller as claimed in claim 1 ,
wherein the length comprises a first period in a first situation and a second period different from the first period in a second situation.
6. A controller, comprising:
a system clock terminal configured to correspond to a system clock to which a semiconductor memory device receives, the system clock having a first frequency or a second frequency;
a first external terminal configured to communicate a data;
a second external terminal configured to communicate a data strobe signal related to the data, the data strobe signal including a preamble and a toggle transition following to the preamble, the data being transferred by the toggle transition of the data strobe signal through the first external terminal; and
a third external terminal configured to be capable of outputting an information which specifies a length of the preamble, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.
7. The controller as claimed in claim 6 , the controller further comprising:
a preamble length determination unit configured to determine the length of the preamble.
8. The controller as claimed in claim 7 ,
wherein the preamble length determination unit determines the length of the preamble based on a frequency of the system clock.
9. The controller as claimed in claim 6 , the controller further comprising:
a plurality of external terminals configured to output an address strobe signal, and a write enable signal.
10. The controller as claimed in claim 9 ,
wherein the plurality of external terminals further outputs a clock enable signal and a chip select signal.
11. The controller as claimed in claim 6 ,
wherein the length is 1CK of the system clock in a first situation and 2CK of the system clock in a second situation.
12. The controller as claimed in claim 6 ,
wherein the length comprises a first period in a first situation and a second period different from the first period in a second situation.
13. The controller as claimed in claim 1 , the controller further comprising a determination unit that determines a value tRPRE to be set as the information of the length, wherein said deteimination unit sets said value tRPRE as satisfying the condition that tse >0 in the following expression:
tse=tRPRE− ( tDQSCK max− tDQSCK min),
where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DQS terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.
14. The controller as claimed in claim 1 , wherein the more the frequency of the system clock is increased, the longer the length of the preamble is.
15. The controller as claimed in claim 14 , wherein the larger a CAS latency is, the longer the length of the preamble is.
16. The controller as claimed in claim 14 , wherein the length of the preamble is changed enough that the controller includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.
17. The controller as claimed in claim 6 , the controller further comprising a determination unit that determines a value tRPRE to be set as the information of the length, wherein said determination unit sets said value tRPRE as satisfying the condition that tse >0 in the following expression:
tse=tRPRE− ( tDQSCK max− tDQSCK min),
where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DQS terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.
18. The controller as claimed in claim 6 , wherein the more the frequency of the system clock is increased, the longer the length of the preamble is.
19. The controller as claimed in claim 18 , wherein the larger a CAS latency is, the longer the length of the preamble is.
20. The controller as claimed in claim 18 , wherein the length of the preamble is changed enough that the controller includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.