Quad-core camera processor
View Patent ↗A quad-core processor for a camera with a CMOS image sensor. The quad-core processor has an image sensor interface for receiving data from the CMOS image sensor and four processing units configured for operating in parallel to process the data from the image sensor interface. The four processing units and the image sensor interface are integrated onto a single chip.
1. A processor for a device that includes a camera, the processor comprising:
an image sensor interface for receiving data from an image sensor associated with the camera;
multiple processing units configured for operating in parallel to process the data from the image sensor interface, wherein a data transfer channel is directly coupled to each of the multiple processing units for the transmission of data, such data transfer channel being separate and independent from a dedicated processing channel connected between the multiple processing units that provides a pathway for communication among the multiple processors during parallel processing; and
a plurality of interfaces for transmitting data processed by the multiple processing units to functional components within the device through such data transfer channel, wherein each processing unit of the multiple processing units includes at least one address generator for addressing processed data for transmission to the functional components through such data transfer channel;
wherein the multiple processing units, the plurality of interfaces, and the image sensor interface are integrated onto a single chip.
2. The processor according to claim 1 , further comprising:
an input FIFO (first in, first out) for receiving the data from the image sensor interface and inputting the data to the multiple processing units, and
an output FIFO for receiving the data processed by the multiple processing units.
3. The processor according to claim 1 , further comprising a crossbar switch for connecting each of the multiple processing units.
4. The processor according to claim 2 , wherein the multiple processing units are connected to the output FIFO, the output FIFO being configured to hold the data processed by the multiple processing units until read by the functional components.
5. The processor according to claim 1 , further comprising a central processing unit for controlling each of the multiple processing units, each of the multiple processing units having RAM (random access memory) in which the central processing unit writes microcode to govern the operation of the processing unit.
6. The processor according to claim 1 , wherein the data received from the image sensor is input image data and the multiple processing units perform one or more processing tasks selected from:
rotating the input image data;
color converting the input image data; and
dithering the input image data.
7. The processor according to claim 1 , further comprising a data cache connected to the multiple processing units for storing the data processed by the multiple processing units.
8. The processor according to claim 1 , further comprising a display interface, wherein the data processed by the multiple processing units includes screen image data addressed to the display interface.
9. The processor according to claim 5 , wherein the plurality of interfaces includes a keyboard interface for receiving user input that causes the central processing unit to rewrite the microcode in the RAM within each of the multiple processing units.
10. The processor according to claim 1 , wherein the plurality of interfaces includes a first interface for receiving encoded data indicative of an image processing instruction in a machine readable form, the first interface being configured to decode the encoded data corresponding to the image processing instruction.
11. The processor according to claim 1 , wherein the plurality of interfaces includes one or more of a USB (Universal Serial Port) interface, an infra-red interface, a display interface, and a keyboard interface.
12. A hand held imaging device, comprising:
an image sensor; and
a processor, comprising:
an image sensor interface for receiving data from the image sensor,
multiple processing units configured for operating in parallel to process the data from the image sensor interface, wherein a data transfer channel is directly coupled to each of the multiple processing units for the transmission of data, such data transfer channel being separate and independent from a dedicated processing channel connected between the multiple processing units that provides a pathway for communication among the multiple processors during parallel processing, and
a plurality of interfaces for transmitting data processed by the multiple processing units to functional components through such data transfer channel within the device, wherein each processing unit of the multiple processing units includes at least one address generator for addressing processed data for transmission to the functional components through such data transfer channel,
wherein the multiple processing units, the plurality of interfaces, and the image sensor interface are integrated onto a single chip.
13. The hand held imaging device according to claim 12 , wherein the processor further comprises:
an input FIFO (first in, first out) for receiving the data from the image sensor interface and inputting the data to the multiple processing units; and
an output FIFO for receiving the data processed by the multiple processing units.
14. The hand held imaging device according to claim 13 , wherein the multiple processing units are connected to the output FIFO, the output FIFO being configured to hold the data processed by the multiple processing units until read by the functional components.
15. The hand held imaging device according to claim 12 , wherein the processor further comprises a crossbar switch for connecting each of the multiple processing units.
16. The hand held imaging device according to claim 12 , wherein the processor further comprises a central processing unit for controlling each of the multiple processing units, each of the multiple processing units having RAM (random access memory) in which the central processing unit writes microcode to govern the operation of the processing unit.
17. The hand held imaging device according to claim 16 , wherein the plurality of interfaces includes a keyboard interface for receiving user input that causes the central processing unit to rewrite the microcode in the RAM within each of the multiple processing units.
18. The hand held imaging device according to claim 12 , wherein the processor further comprises a data cache connected to the multiple processing units for storing the data processed by the multiple processing units.
19. The hand held imaging device according to claim 12 , wherein the processor further comprises a display interface, wherein the data processed by the multiple processing units includes screen image data addressed to the display interface.
20. The hand held imaging device according to claim 12 , wherein the plurality of interfaces includes a first interface for receiving encoded data indicative of an image processing instruction in a machine readable form, the first interface being configured to decode the encoded data corresponding to the image processing instruction.