Camera with linked parallel processor cores
View Patent ↗A camera with a CMOS image sensor, an image sensor interface for receiving data from the CMOS image sensor and multiple processing units interconnected with each other for parallel processing of data from the image sensor interface. The multiple processing units and the image sensor interface are integrated onto a single chip.
1. An electronic device, comprising:
an image sensor;
an image sensor interface for receiving input data from the image sensor;
an instruction input interface configured to receive a signal and decode the signal into image processing instructions, wherein an example image corresponding to the image processing instructions comprises an image distorted by a particular effect of executing the image processing instructions; and
multiple processing units interconnected with each other for parallel processing of data from the image sensor interface to generate an output image based on distorting an input image corresponding to the input data by the particular effect.
2. The electronic device according to claim 1 , wherein each of the multiple processing units includes rewritable memory storing microcode to operatively control the processing unit.
3. The camera according to claim 1 , wherein the signal is based on a pattern in a machine readable form.
4. The electronic device according to claim 1 , further comprising:
a crossbar switch, wherein the crossbar switch interconnects each of the multiple processing units.
5. The electronic device according to claim 4 , further comprising:
an input FIFO (first in, first out) configured for receiving data from the image sensor interface and inputting the data to the multiple processing units; and
an output FIFO configured for receiving processed data to be read by other components of the electronic device.
6. The electronic device according to claim 5 , further comprising:
a central processing unit configured to operatively control the multiple processing units; and
a data bus configured to connect the central processing unit to the input FIFO and the output FIFO.
7. The electronic device according to claim 6 , further comprising:
a data cache configured to store the processed data until required by the central processing unit.
8. The electronic device according to claim 1 , wherein the multiple processing units perform one or more processing tasks selected from:
rotating the input image;
color converting the input image; and
dithering the input image.
9. The electronic device according to claim 1 , further comprising:
a display; and
a display interface, the display interface being connected to a data cache for reading processed data and transmitting the processed data to the display.
10. The electronic device according to claim 9 , wherein each of the multiple processing units includes at least one address generator for the processed data sent to the data cache.
11. The electronic device according to claim 2 , further comprising:
a keyboard interface configured for user input of instructions for rewriting the rewritable memory within each of the processing units.
12. A processor, comprising:
an image sensor interface for receiving input data from an image sensor;
an instruction input interface configured to receive a signal and decode the signal into image processing instructions, wherein an example image corresponding to the image processing instructions comprises an image distorted by a particular effect of executing the image processing instructions; and
multiple processing units interconnected with each other for parallel processing of data from the image sensor interface to generate an output image based on distorting an input image corresponding to the input data by the particular effect.
13. The processor according to claim 12 , further comprising a crossbar switch for interconnecting each of the multiple processing units.
14. The processor according to claim 12 , further comprising:
an input FIFO (first in, first out) configured to receive data from the first and second image sensor interfaces and input the data to the multiple processing units; and
an output FIFO configured to receive processed data to be read by other components of an electronic device that includes the processor.
15. The processor according to claim 14 , further comprising:
a central processing unit; and
a data bus connecting the central processing unit to the input FIFO and the output FIFO, the central processing unit providing a processing core to operatively control the multiple processing units.
16. The processor according to claim 15 , wherein each of the multiple processing units has RAM (random access memory) for storing microcode written by the central processing unit to operatively control the processing unit.
17. The processor according to claim 16 , wherein the processor further includes a keyboard interface for user input of instructions to the central processing unit such that the central processing unit rewrites the microcode in the RAM within each of the multiple processing units.
18. The processor according to claim 15 , further comprising a data cache to store the processed data until required by the central processing unit.
19. The electronic device according to claim 18 , wherein each of the multiple processing units includes at least one address generator for the processed data sent to the data cache.
20. The electronic device according to claim 12 , wherein the signal is based on a pattern in a machine readable form.