Multi-core image processor for portable device
View Patent ↗A processor for a portable handheld device having an area image sensor includes a shared wafer substrate; an image sensor interface provided on the shared wafer substrate, the image sensor interface for receiving image data capture by an image sensor; an image processor provided on the shared wafer substrate, the image processor for processing the image data received by the image sensor interface; a central processor provided on the shared wafer substrate, the central processor for loading the image processor with instructions; a first internal bus provided on the shared wafer substrate, the first internal bus effecting communication between the image sensor interface and the image processor; and a second internal bus provided on the shared wafer substrate, the second internal bus effecting communication between the central processor and the image processor.
1. A processor for a portable device having an area image sensor, the processor comprising:
a shared wafer substrate;
an image sensor interface provided on the shared wafer substrate, the image sensor interface configured for receiving image data captured by an image sensor and sending control information to the image sensor;
a second image sensor interface provided on the shared wafer substrate, the second image sensor interface configured for receiving image data captured by a second image sensor;
an image processor provided on the shared wafer substrate, the image processor configured for processing the image data received by the image sensor interface;
a central processor provided on the shared wafer substrate, the central processor configured for loading the image processor with instructions;
a first internal bus provided on the shared wafer substrate, the first internal bus effecting communication between the image sensor interface and the image processor; and
a second internal bus provided on the shared wafer substrate, the second internal bus effecting communication between the central processor and the image processor.
2. The processor of claim 1 , wherein the image processor includes a plurality of processing units connected in parallel via a crossbar switch.
3. The processor of claim 2 , wherein each processing unit includes an instruction memory for storing therein the instructions loaded by the central processor.
4. The processor of claim 3 , further comprising a flash memory provided on the shared wafer substrate, the flash memory configured for storing microcode instructions, wherein the flash memory is read by the central processor to obtain therefrom microcode instructions for loading into the instruction memory of each processing unit.
5. The processor of claim 2 , further comprising a data cache provided on the shared wafer substrate, the data cache being shared by the plurality of processing units via a data bus.
6. The processor of claim 5 , wherein each processing unit includes an input buffer and an output buffer disposed internally within the processing unit, both the input buffer and the output buffer being connected to the data bus to effect connection with the data cache.
7. The processor of claim 2 , wherein each processing unit includes an ALU, each ALU being connected to the crossbar switch to effect parallel connection of the processing units.
8. The processor of claim 1 , wherein the control information comprises a frame sync pulse and a pixel clock.
9. The processor of claim 1 , wherein the second image sensor interface is configured to send second image sensor control information to the second image sensor.
10. The processor of claim 9 , wherein the second image sensor control information comprises a line sync pulse and a pixel clock pulse.