Handheld imaging device with image processor provided with multiple parallel processing units

1. A portable imaging device, comprising:

an image sensor configured for sensing an image and generating image data related to the image;

a micro-controller integrating therein a dedicated image processor for processing the image data, a bus interface, and an image sensor interface;

a plurality of processing units connected in parallel, the plurality of processing units provided within the micro-controller to form a multi-core processing unit for the micro-controller;

a memory configured for storing data addressed by the plurality of processing units;

a data cache provided within the micro-controller and connected to the plurality of processing units via a plurality of buses, wherein

the image sensor interface provides communication between the micro-controller and the image sensor,

the bus interface provides communication between the micro-controller and devices external to the micro-controller other than the image sensor, and

the data cache is disposed between the plurality of processing units and the memory.

2. The device according to claim 1 , further comprising an input buffer in communication with the plurality of processing units, the input buffer for receiving data bound for the plurality of processing units and configured for sharing by each of the plurality of processing units.

3. The device according to claim 1 , further comprising an output buffer in communication with the plurality of processing units, the output buffer for receiving data processed by the plurality of processing units and configured for sharing by each of the plurality of processing units.

4. The device according to claim 1 , further comprising a card scanner for scanning a surface of a card for the presence of dots printed thereon.

5. The device according to claim 4 , further comprising a card scanner interface for receiving from the card scanner data indicative of the presence of dots scanned from the surface of the card, and decoding the dots into an image processing script.

6. The device according to claim 5 , further comprising a CPU for executing an image processing language interpreter on the image processing script, and providing instructions to the dedicated image processor to process the image data in accordance with the image processing script.

7. The device according to claim 3 , further comprising a print head interface, the print head interface for reading dither-formatted data from the output buffer and passing the dither-formatted data to a print head.

8. The device according to claim 1 , wherein the image sensor is a charge-coupled device (CCD), and the image sensor interface includes an analogue/digital converter for converting signals passing between the processor and the CCD.

9. The device according to claim 1 , wherein each of the plurality of processing units includes two I/O address generator, and each I/O address generator is connected to a respective one of the plurality of buses.

10. The device according to claim 1 , further comprising a printer for printing out the sensed image.

11. The device according to claim 10 , wherein the micro-controller further integrates therein a print head interface for receiving print data from the plurality of processing units, and sending the print head to the printer.

12. The device according to claim 1 , wherein the image sensor interface is configured for:

receiving the image data from the image sensor;

converting the image data to a format readable by the plurality of processing units; and

providing control information from the micro-controller to the image sensor.

13. The processor of claim 12 , wherein the control information comprises a frame sync pulse and a pixel clock.

14. The device according to claim 9 , wherein the memory is disposed external to the micro-controller and the two I/O address generators of each of the plurality of processing units are configured for controlling a transfer of data from the image sensor interface to and from the memory.

15. The device according to claim 14 , wherein the two I/O address generators of each of the plurality of processing units controls the transfer of the data from the image sensor interface to and from the data cache.

16. The device according to claim 15 , wherein the micro-controller further comprises a memory interface separate from the image sensor interface and configured to provide an interface between the data cache and the memory.

17. The device according to claim 1 , wherein the plurality of processing units are connected in parallel by a crossbar switch.