Handheld imaging device with multi-core image processor integrating image sensor interface

1. A portable imaging device, comprising:

an image sensor configured to generate signals carrying data relating to an image sensed by the image sensor;

a processor configured for processing the data relating to the image sensed by the image sensor;

a multi-core processing unit provided in the processor, the multi-core processing unit having a plurality of processing units connected in parallel by a crossbar switch;

an image sensor interface for converting the signals to a format readable by the multi-core processing unit and providing control information to the image sensor, the image sensor interface sharing a wafer substrate with the processors;

a data cache connected to the plurality of processing units via a plurality of buses separate from the crossbar switch; and

an external memory configured to store the data relating to the image sensed by the image sensor, wherein:

a transfer of data from the image sensor interface to the plurality of processing units is conducted entirely on the shared wafer substrate,

each of the plurality of processing units includes two I/O address generators, and each I/O address generator of the two I/O address generators is connected to a respective one of the plurality of buses, and

the two I/O address generators of each of the plurality of processing units are configured to control a transfer of the data from the image sensor interface to and from the external memory.

2. The device according to claim 1 , further comprising an input buffer provided on the shared wafer substrate and in communication with the crossbar switch, the input buffer for receiving data bound for the plurality of processing units and configured for sharing by each of the plurality of processing units.

3. The device according to claim 1 , further comprising an output buffer provided on the shared wafer substrate and in communication with the crossbar switch, the output buffer for receiving data processed by the plurality of processing units and configured for sharing by each of the plurality of processing units.

4. The device according to claim 1 , further comprising a scanner for scanning for a presence of a pattern.

5. The device according to claim 4 , further comprising a scanner interface for receiving from the scanner data indicative of the presence of the pattern, wherein the pattern defines an image processing script.

6. The device according to claim 5 , further comprising a CPU for executing an image processing language interpreter on the image processing script, and providing instructions to the multi-core processor to process the data relating to the image sensed by the image sensor in accordance with the image processing script.

7. The device according to claim 3 , further comprising a print head interface, the print head interface for reading dither-formatted data from the output buffer and passing the dither-formatted data to a print head.

8. The device according to claim 1 , wherein the image sensor is a charge-coupled device (CCD), and the image sensor interface includes an analogue/digital converter for converting signals passing between the processor and the CCD.

9. The device according to claim 1 , further comprising a printer for printing out the sensed image.

10. The device according to claim 9 , further comprising, on the shared wafer substrate, a print head interface for receiving print data from the plurality of processing units, and sending the print head to the printer.

11. The processor of claim 1 , wherein the control information comprises a frame sync pulse and a pixel clock.

12. The device according to claim 1 , wherein the data cache is disposed between the external memory and the plurality of processing units, and the data cache shares the wafer substrate with the processor.

13. The device according to claim 12 , wherein the two I/O address generators of each of the plurality of processing units controls the transfer of data from the image sensor interface to and from the data cache.

14. The device according to claim 13 , further comprising a memory interface separate from the image sensor interface and configured to provide an interface between the data cache and the external memory, wherein the memory interface shares the wafer substrate with the processor.