Portable device with dual image sensors and quad-core processor
View Patent ↗A portable device that has first and second image sensors and a central processor. The central processor has four processing units and a first image sensor interface and a second image sensor interface for receiving data from the from the first and second image sensors respectively. The four processing units and the first and second sensor interfaces are integrated onto a single chip such that the four processing units are configured to simultaneously process the data from the first and second image interfaces to generate stereoscopic image data.
1. An electronic device, comprising:
a first image sensor;
a second image sensor; and
a processor including:
a first image sensor interface for receiving data from the from the first image sensor,
a second image sensor interface for receiving data from the from the second image sensor,
multiple processing units configured to process data in parallel based on executing image processing instructions, and
an instruction input interface configured to receive a signal based on a pattern and to decode the signal into the image processing instructions,
wherein the multiple processing units are configured to simultaneously process the data from the first and second image interfaces to generate stereoscopic image data.
2. The electronic device according to claim 1 , wherein the processor further comprises a crossbar switch for interconnecting each of the multiple processing units.
3. The electronic device according to claim 1 , wherein the processor further includes:
an input FIFO (first in, first out) configured to receive data from the first and second image sensor interfaces and input the data to the multiple processing units; and
an output FIFO configured to receive processed data to be read by other components of the electronic device.
4. The electronic device according to claim 3 , wherein the processor further includes:
a central processing unit; and
a data bus connecting the central processing unit to the input FIFO and the output FIFO, the central processing unit providing a processing core to operatively control the multiple processing units.
5. The electronic device according to claim 4 , wherein the processor further includes a data cache to store the processed data until required by the central processing unit.
6. The electronic device according to claim 1 , wherein the multiple processing units are further configured to perform one or more processing tasks selected from:
rotating the data received from the first and second image sensors;
color converting the data received from the first and second image sensors; and
dithering the data received from the first and second image sensors.
7. The electronic device according to claim 1 , further comprising a display for viewing an image captured by the first and second image sensors, wherein the processor further includes a display interface for transmitting processed data to the display.
8. The electronic device according to claim 5 , wherein each of the multiple processing units includes at least one address generator for the processed data sent to the data cache.
9. The electronic device according to claim 4 , wherein each of the multiple processing units has RAM (random access memory) for storing microcode written by the central processing unit to operatively control the processing unit.
10. The electronic device according to claim 9 , wherein the processor further includes a keyboard interface for user input of instructions to the central processing unit such that the central processing unit rewrites the microcode in the RAM within each of the multiple processing units.
11. The electronic device according to claim 1 , further comprising a USB port for communication with an external device, wherein the processor further comprises a USB interface.
12. The electronic device according to claim 1 , further comprising a 3 Volt battery.
13. A processor, comprising:
a first image sensor interface for receiving data from a first image sensor;
a second image sensor interface for receiving data from a second image sensor;
multiple processing units configured to process data in parallel based on executing image processing instructions; and
an instruction input interface configured to receive a signal based on a pattern and to decode the signal into the image processing instructions,
wherein the multiple processing units are configured to simultaneously process the data from the first and second image interfaces to generate stereoscopic image data.
14. The processor according to claim 13 , further comprising a crossbar switch for interconnecting each of the multiple processing units.
15. The processor according to claim 13 , further comprising:
an input FIFO (first in, first out) configured to receive data from the first and second image sensor interfaces and input the data to the multiple processing units; and
an output FIFO configured to receive processed data to be read by other components of the electronic device.
16. The processor according to claim 15 , further comprising:
a central processing unit; and
a data bus connecting the central processing unit to the input FIFO and the output FIFO, the central processing unit providing a processing core to operatively control the multiple processing units.
17. The processor according to claim 16 , wherein each of the multiple processing units has RAM (random access memory) for storing microcode written by the central processing unit to operatively control the processing unit.
18. The processor according to claim 17 , wherein the processor further includes a keyboard interface for user input of instructions to the central processing unit such that the central processing unit rewrites the microcode in the RAM within each of the multiple processing units.
19. The processor according to claim 16 , further comprising a data cache to store the processed data until required by the central processing unit.
20. The electronic device according to claim 19 , wherein each of the multiple processing units includes at least one address generator for the processed data sent to the data cache.