Multi-core processor for portable device with dual image sensors
View Patent ↗A multi-core processor is used in a portable device that has first and second image sensors spaced from each other for capturing images of a scene from slightly different perspectives. The multi-core processor has a first image sensor interface for receiving data from the image sensor, a second image sensor interface for receiving data from the second image sensor, multiple processing units and, the four processing units and the first and second sensor interfaces being integrated onto a single chip. The processing units are configured to simultaneously process the data from the first and second image interfaces to generate stereoscopic image data.
1. A multi-core processor for an electronic device that includes first and second image sensors spaced from each other for capturing images of a scene from different perspectives, the multi-core processor comprising:
a first image sensor interface for receiving data from the first image sensor;
a second image sensor interface for receiving data from the second image sensor;
multiple processing units configured to execute image processing instructions to simultaneously process the data received by the first and second image sensor interfaces to generate stereoscopic image data; and
an instruction input interface,
wherein the electronic device further includes an input device for receiving an input that corresponds to machine-readable data, and
wherein the instruction input interface is configured to receive the machine-readable data, decode the machine-readable data into the image processing instructions, and input the image processing instructions to the multiple processing units.
2. The multi-core processor according to claim h wherein the electronic device further includes a display for viewing an image captured by at least one of the first or second image sensors, and the multi-core processor further comprises a display interface for transmitting data processed by the multiple processing units to the display.
3. The multi-core processor according to claim 2 , wherein each of the multiple processing units includes at least one address generator for the data processed by the multiple processing units.
4. The multi-core processor according to claim 1 , wherein each of the multiple processing units has RAM (random access memory) for microcode written to the RAM for operative control of the processing unit.
5. The multi-core processor according to claim 4 , further comprising a central processing unit configured to write microcode to the RAM in each of the multiple processing units.
6. The multi-core processor according to claim 5 , further comprising a keyboard interface for user input of instructions to the central processing unit such that the central processing unit rewrites the microcode in the RAM within each of the multiple processing units.
7. The multi-core processor according to claim 1 , further comprising a crossbar switch for interconnecting each of the multiple processing units.
8. The multi-core processor according to claim 1 , further comprising:
an input FIFO (first in, first out) configured for receiving data from the first and second image sensor interfaces and inputting the data to the multiple processing units, and
an output FIFO configured for receiving data processed by the multi processing units to be read by other components of the electronic device.
9. The multi-core processor according to claim 8 , further comprising a data bus connecting a central processing unit to the input FIFO and the output FIFO.
10. The multi-core processor according to claim 9 , further comprising a data cache to store the data processed by the multiple processing units until required by the central processing unit.
11. The multi-core processor according to claim 1 , wherein the multiple processing units are further configured to perform one or more processing tasks selected from:
rotating the data received by the first and second image sensor interfaces;
color converting the data received by the first and second image sensor interfaces; and
dithering the data received by the first and second image sensor interfaces.
12. The multi-core processor according to claim 1 , wherein the electronic device further includes a USB port for communication with an external device, and the multi-core processor further comprises a USB interface in communication with the USB port.
13. The multi-core processor according to claim 1 , wherein the multiple processing units are configured to operate using a 1.5V power supply.
14. A electronic device, comprising:
a first image sensor configured to capture an image of a scene;
a second image sensor spaced from the first image sensor to capture an image of the scene from a different perspective than the first image sensor;
an input device for receiving an input that corresponds to machine-readable data; and
a processing system, including:
a first image sensor interface for receiving data from the first image sensor,
a second image sensor interface for receiving data from the second image sensor,
multiple processing units configured to execute image processing instructions to simultaneously process the data received by the first and second image sensor interfaces to generate stereoscopic image data, and
an instruction input interface configured to receive the machine-readable data from the input device, decode the machine-readable data into the image processing instructions, and input the image processing instructions to the multiple processing units.
15. The electronic device according to claim 14 , further comprising:
a display for viewing an image captured by at least one of the first or second image sensors,
wherein the multi-core processor further comprises a display interface for transmitting data processed by the multiple processing units to the display.
16. The electronic device according to claim 15 , wherein each of the multiple processing units includes at least one address generator for the data processed by the multiple processing units.
17. The electronic device according to claim 14 , wherein each of the multiple processing units has RAM (random access memory) for microcode written to the RAM for operative control of the processing unit.
18. The electronic device according to claim 17 , wherein the processing system further comprises a central processing unit configured to write microcode to the RAM in each of the multiple processing units.
19. The electronic device according to claim 14 , wherein the processing system further comprises a crossbar switch for interconnecting each of the multiple processing units.
20. The electronic device according to claim 14 , wherein the processing system further comprises:
an input FIFO (first in, first out) configured for receiving data from the first and second image sensor interfaces and inputting the data to the multiple processing units; and
an output FIFO configured for receiving data processed by the multiple processing units to be read by other components of the electronic device.