Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
View Patent ↗A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.
1. A semiconductor memory device, comprising:
a system clock terminal provided to receive a system clock with a first frequency or a second frequency;
a data terminal provided to transfer a data therethrough in synchronization with the system clock;
a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough;
a command terminal provided to receive a command that communicates the data with an outside thereof; and
an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.
2. The semiconductor memory device as claimed in claim 1 , the device further comprising:
a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the data strobe signal to communicate the data.
3. The semiconductor memory device as claimed in claim 1 ,
wherein the length of the preamble is the first length when the information indicates a first value.
4. The semiconductor memory device as claimed in claim 3 ,
wherein the length of the preamble is the second length different from the first length when the information indicates a second value different from the first value.
5. The semiconductor memory device as claimed in claim 1 ,
wherein the preamble comprises a read preamble.
6. The semiconductor memory device as claimed in claim 5 ,
wherein the strobe signal comprises a read data strobe signal.
7. The semiconductor memory device as claimed in claim 1 ,
wherein the strobe signal is transferred from the semiconductor memory device to a controller when performing a read operation.
8. The semiconductor memory device as claimed in claim 2 ,
wherein the data strobe signal output control circuit further outputs a postamble of the data strobe signal following to the toggle transition.
9. A semiconductor memory device, comprising:
a first external terminal configured to receive a system clock with a first frequency or a second frequency;
a second external terminal configured to receive a read command in synchronization with the system clock;
a third external terminal configured to output a data strobe signal in response to the read command, the data strobe signal including a preamble and a toggle transition following to the preamble;
a fourth external terminal configured to output a read data in synchronization with the toggle transition of the data strobe signal;
a fifth external terminal configured to receive a preamble length information; and
a control circuit configured to control a length of the preamble of the data strobe signal based on the preamble length information, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.
10. The semiconductor memory device as claimed in claim 9 ,
wherein the length of the preamble is set to the first length when the information indicates a first value.
11. The semiconductor memory device as claimed in claim 10 ,
wherein the length of the preamble is set to the second length different from the first length when the information indicates a second value different from the first value.
12. The semiconductor memory device as claimed in claim 9 ,
wherein the preamble comprises a read preamble.
13. The semiconductor memory device as claimed in claim 12 ,
wherein the strobe signal comprises a read data strobe signal.
14. The semiconductor memory device as claimed in claim 9 , further comprising a CAS latency specification register configured to specify a timing of starting an output of said read data.
15. The semiconductor memory device as claimed in claim 14 , further comprising:
a read flag that is set when said read command is received.
16. A semiconductor memory device, comprising:
a first external terminal provided to receive a system clock with a frequency;
a second external terminal provided to transfer a data therethrough in synchronization with the system clock;
a third external terminal provided to receive a command for communicating the data with an outside thereof;
a control circuit configured to produce a data strobe signal, which includes a preamble and a toggle transition following to the preamble, so that the transferring the data is conducted by the toggle transition of the data strobe signal; and
a fourth external terminal provided to be supplied an information specifying a length of the preamble of the strobe signal from an outside of the semiconductor memory device, the length of the preamble being changed based on the frequency of the system clock, the length being defined by a number of clock of the system clock.
17. The semiconductor memory device as claimed in claim 16 ,
wherein the length of the preamble is a first length when the information indicates a first value.
18. The semiconductor memory device as claimed in claim 17 ,
wherein the length of the preamble is a second length different from the first length when the information indicates a second value different from the first value.
19. The semiconductor memory device as claimed in claim 16 ,
wherein the fourth external terminal comprises an address terminal.
20. The semiconductor memory device as claimed in claim 16 ,
wherein the control circuit further receives a CAS latency specification signal.
21. The semiconductor memory device as claimed in claim 16 , wherein the length of the preamble is changed enough that a controller associated to the semiconductor memory device includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.
22. The semiconductor memory device as claimed in claim 16 , further comprising a determination unit that determines a value tRPRE to be set as the information, wherein said determination unit sets said value tRPRE as satisfying the condition that tse>0 in the following expression:
tse=tRPRE−(tDQSCKmax−tDQSCKmin),
where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DQS terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.
23. The semiconductor memory device as claimed in claim 1 , wherein the length of the preamble is changed enough that a controller associated to the semiconductor memory device includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.
24. The semiconductor memory device as claimed in claim 1 , further comprising a determination unit that determines a value tRPRE to be set as the information, wherein said determination unit sets said value tRPRE as satisfying the condition that tse>0 in the following expression:
tse=tRPRE−(tDQSCKmax−tDQSCKmin),
where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DQS terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.
25. The semiconductor memory device as claimed in claim 9 , wherein the length of the preamble is changed enough that a controller associated to the semiconductor memory device includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.
26. The semiconductor memory device as claimed in claim 9 , further comprising a determination unit that determines a value tRPRE to be set as the information, wherein said determination unit sets said value tRPRE as satisfying the condition that tse>0 in the following expression:
tse=tRPRE−(tDQSCKmax−tDQSCKmin),
where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DQS terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.