Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
View Patent ↗A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.
1. A system, comprising:
a semiconductor memory device and a controller,
the semiconductor memory device comprising:
a first external terminal provided to receive a system clock with a first frequency or a second frequency;
a second external terminal provided to receive a read command;
a third external terminal configured to output a data strobe signal in response to the read command, the data strobe signal including a read preamble and a toggle transition following to the read preamble;
a fourth external terminal provided to output a read data in synchronization with the toggle transition of the data strobe signal; and
a control circuit configured to control a length of the read preamble of the data strobe signal based on a preamble length information,
the controller comprising:
a fifth external terminal provided to correspond to the system clock;
a sixth external terminal provided to output the read command;
a seventh external terminal provided to receive the read data;
an eighth external terminal provided to receive the data strobe signal related to the read data; and
a ninth external terminal provided to output the preamble length information, so that the length of the read preamble includes first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.
2. The system as claimed in claim 1 ,
wherein the length of the read preamble is set to the first length when the information indicates a first value.
3. The system as claimed in claim 2 ,
wherein the length of the read preamble is set to the second length different from the first length when the information indicates a second value different from the first value.
4. The system as claimed in claim 1 , the controller further comprising:
a preamble length determination unit configured to determine the length of the read preamble.
5. The system as claimed in claim 4 ,
wherein the preamble length determination unit determines the length of the read preamble based on a variation of a delay time of the strobe signal.
6. The system as claimed in claim 4 ,
wherein the preamble length determination unit determines the length of the read preamble at a system start-up time.
7. The system as claimed in claim 4 ,
wherein the preamble length determination unit determines the length of the read preamble for each fixed time interval.
8. A system, comprising:
a semiconductor memory device and a controller;
the semiconductor memory device comprising:
a first external terminal provided to receive a system clock with a first frequency or a second frequency;
a second external terminal provided to transfer a data with the controller in synchronization with the system clock;
a third external terminal provided to receive a command for communicating the data;
a control circuit configured to produce a data strobe signal, which includes a preamble and a toggle transition following to the preamble, so that the transferring the data is conducted by the toggle transition of the data strobe signal; and
a fourth external terminal provided to be supplied an information specifying a length of the preamble of the strobe signal,
the controller, comprising:
a fifth external terminal provided to correspond to the system clock;
a sixth external terminal provided to communicate the data;
a seventh external terminal configured to output the command; and
an eighth external terminal configured to output the information, so that the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.
9. The system as claimed in claim 8 ,
wherein the length of the preamble is set to the first length when the information indicates a first value, and the length of the preamble is set to the second length different from the first length when the information indicates a second value different from the first value.
10. The system as claimed in claim 8 , the controller further comprising:
a preamble length determination unit configured to determine the length of the preamble.
11. The system as claimed in claim 8 ,
wherein the data strobe signal is transferred from the semiconductor memory device to the controller when performing a read operation.
12. The system as claimed in claim 1 , further comprising a determination unit that determines a value tRPRE to be set as the information of the length, wherein said determination unit sets said value tRPRE as satisfying the condition that tse>0 in the following expression:
tse=tRPRE −( tDQSCK max− tDQSCK min),
where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DQS terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.
13. The system as claimed in claim 1 , wherein the more the frequency of the system clock is increased, the longer the length of the read preamble is.
14. The system as claimed in claim 13 , wherein the larger a CAS latency is, the longer the length of the read preamble is.
15. The system as claimed in claim 13 , wherein the length of the read preamble is changed enough that the controller includes a gate opening area, which overlaps the length of the read preamble, so that the controller can receive the data from the memory device.
16. The system as claimed in claim 8 , further comprising a determination unit that determines a value tRPRE to be set as the information of the length, wherein said determination unit sets said value tRPRE as satisfying the condition that tse>0 in the following expression:
tse=tRPRE −( tDQSCK max− tDQSCK min),
where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DQS terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.
17. The system as claimed in claim 8 , wherein the more the frequency of the system clock is increased, the longer the length of the preamble is.
18. The system as claimed in claim 17 , wherein the larger a CAS latency is, the longer the length of the preamble is.
19. The system as claimed in claim 17 , wherein the length of the preamble is changed enough that the controller includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.