IP Library Granted Patent US 8,987,807
Granted Patent B2
US 8,987,807 · App. 13/622,612 · Granted Mar 24, 2015

Nonvolatile semiconductor memory device and method of manufacturing the same

Inventors: Shosuke Fujii (Yokohama, JP); Kiwamu Sakuma (Yokohama, JP); Jun Fujiki (Yokohama, JP); Atsuhiro Kinoshita (Kamakura, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/11551H01L27/11521H01L27/11578H01L27/11519H01L27/11565
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Quick Facts
Patent No.
US 8,987,807
App. No.
13/622,612
Granted
Mar 24, 2015
Kind
B2
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.

Claims (41)

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

first to n-th semiconductor layers (n is a natural number equal to or more than 2) which are stacked in a first direction perpendicular to a surface of the semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate;

an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions; and

first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively,

wherein the first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.

2. The device of claim 1 ,

wherein the uppermost layer among the first to n-th semiconductor layers is a dummy layer in which dummy cells as non-memory cells are provided.

3. The device of claim 2 ,

wherein a width of the uppermost layer in the first direction is wider than a width of the semiconductor layer except the uppermost layer in the first direction.

4. The device of claim 1 ,

wherein the first to n-th charge storage layers are separated by insulators between the first to n-th semiconductor layers.

5. The device of claim 1 ,

wherein the first to n-th charge storage layers comprise materials respectively, and the first to n-th charge storage layers are separated by oxides of the materials.

6. The device of claim 1 ,

wherein the first to n-th charge storage layers are separated by cavities between the first to n-th semiconductor layers.

7. The device of claim 1 ,

wherein the first to n-th charge storage layers are silicon nitride, and are separated by silicon oxynitride.

8. The device of claim 1 ,

wherein the first to n-th charge storage layers are covered with the electrode and are independently each other.

9. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

semiconductor layers which are stacked in a first direction perpendicular to a surface of the semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate; and

memory strings which use the semiconductor layers as channels respectively,

wherein the memory strings comprises electrodes which extend in the first direction along side surfaces of the semiconductor layers and charge storage layers located between the semiconductor layers and the electrodes respectively,

the side surfaces of the semiconductor layers are exposed in a third direction perpendicular to the first and second directions, and

the charge storage layers are separated from each other in areas between the semiconductor layers.

10. The device of claim 9 ,

wherein the uppermost layer among the semiconductor layers is a dummy layer in which dummy cells as non-memory cells are provided.

11. The device of claim 10 ,

wherein a width of the uppermost layer in the first direction is wider than a width of the semiconductor layer except the uppermost layer in the first direction.

12. The device of claim 10 ,

wherein the charge storage layers are separated by insulators between the semiconductor layers.

13. The device of claim 9 ,

wherein the first to n-th charge storage layers comprise materials respectively, and the first to n-th charge storage layers are separated by oxides of the materials.

14. The device of claim 9 ,

wherein the charge storage layers are separated by cavities between the semiconductor layers.

15. The device of claim 9 ,

wherein the charge storage layers are silicon nitride, and are separated by silicon oxynitride.

16. The device of claim 9 ,

wherein the charge storage layers are covered with the electrodes and are independently each other.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2012
From: FUJII, SHOSUKE; SAKUMA, KIWAMU; FUJIKI, JUN; KINOSHITA, ATSUHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 029509/0500 →
Continuity (2)
Continuation PCTJP2010054771 · Mar 19, 2010
Related Publication 20130015519A1 · Jan 17, 2013