System and method for high-performance, low-power data center interconnect fabric with addressing and unicast routing
View Patent ↗A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
1. A method comprising:
generating an escape route from a first node to a second node in a switch fabric, wherein the escape route is an alternate, non-desirable route from the first node to the second node that has a lower priority weight than a desirable route, wherein the escape route violates routing rules of the desirable route, and wherein the switch fabric includes a plurality of nodes and a plurality of links to form a plurality of routes; and
misrouting data from the first node to the second node in response to a link between the first and second nodes being inactive, wherein the escape route and misrouting provide fault tolerance to the switch fabric, and wherein said misrouting includes:
setting, when a node in a data path does not have a link path to the second node, a misrouting bit in a header associated with the data, wherein the misrouting bit indicates an identity of the node in the data path that does not have the link path to the second node.
2. The method of claim 1 , wherein said misrouting data from the first node to the second node further comprises iteratively backtracking to route data from the first node to the second node through one or more intervening nodes if the link between the first and second nodes is inactive.
3. The method of claim 2 , wherein said iteratively backtracking further comprises:
sending the data back to an originating node that sent the data;
choosing one or more alternate links, by the originating node, for the data such that the node in the data path indicated by the misrouting bit is avoided; and
clearing the misrouting bit in a header of the data if the data reaches the second node over one of the one or more alternative links.
4. A switch system, comprising:
a plurality of nodes;
a plurality of links associated with each node that connect the node to another node in the plurality of nodes to create a topology of a switch fabric configured to route data through the plurality of nodes;
a management processor configured to control the routing of data through the switch fabric;
at least one routing header processor configured to generate a routing frame header for an Ethernet frame packet based on a routing table, wherein the routing table includes a path cost and weights for each link to permit adaptive routing of data packets, and wherein the at least one routing header processor is further configured to check an adaptive register to determine whether to do adaptive or deterministic routing; and
a content addressable memory device configured to store a lookup table, wherein a single entry in the lookup table includes four or more contiguous MAC addresses in a single row of the lookup table, and wherein the entry includes an encoded port identification number.
5. The method of claim 1 , wherein the low priority weight is not a lowest possible weight value.
6. The switch system of claim 4 , wherein a weight for a link comprises two bits.
7. The switch system of claim 4 , wherein a given weight value indicates that there is no route between two nodes.
8. The switch system of claim 4 , wherein a given weight value indicates that there is a direct connection between two nodes.
9. The switch system of claim 4 , wherein the weights are in the form of a link weight vector.
10. The switch system of claim 4 , wherein the routing table includes a link encoded unicast entry such that a particular Ethernet frame packet can be communicated over a specific link to a destination node, wherein the link encoded unicast entry comprises twelve bits, and wherein three of the twelve bits indicate a link identification number and two of the twelve bits indicate a port identification number.
11. The switch system of claim 4 , wherein the routing table includes a mapping of a non-switch fabric address to a node.
12. The switch system of claim 4 , wherein:
in a first state, the adaptive register indicates that deterministic routing is to be used such that a first link of the plurality of links is chosen based on a prioritized candidate list; and
in a second state, the adaptive register indicates that adaptive routing is to be used such that a target link of the plurality of links is chosen based on a candidate list and at least:
a round robin pattern used for selecting the target link from the candidate list;
a FIFO (first in, first out) free depth of the target link; or
a link speed of the target link.
13. The switch system of claim 10 , wherein the routing table further includes identifiers to identify MAC address type.
14. The switch system of claim 13 , wherein the MAC address type comprises a node encoded address type or a link encoded address type.
15. The switch system of claim 13 , wherein the identifiers are configured in two registers.
16. The switch system of claim 15 , wherein the two registers are configured to default to standard values during hardware initialization.
17. The switch system of claim 13 , wherein the at least one routing header processor is further configured to modify the identifiers.