Dynamic prescaling counters
View Patent ↗A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.
1. A prescaling counter, comprising
a prescaling unit that includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value; and
a counter having a register that includes a lower count register and an upper count register for generating a count result, wherein the counter is arranged to increment the lower count register in response to the prescaled clock, wherein the counter arranged to increment the upper count register in response to a terminal condition in the lower count register; and wherein the prescaling value is generated in response to the upper count register.
2. The device of claim 1 , wherein the prescaling value is generated in response to an exponentiation function that uses the upper count register as input to the exponentiation function.
3. The device of claim 1 , wherein the counter is arranged to normalize the lower count register in response to the terminal condition.
4. The device of claim 3 , wherein the lower count register is normalized by setting a value of the lower count register to around half of the maximum total of the lower count register.
5. The device of claim 4 , wherein the count result is obtained before an occurrence of the terminal condition by reading the lower count register.
6. The device of claim 4 , wherein the count result is obtained after an occurrence of the terminal condition by reading the lower count register and the upper count register.
7. The device of claim 6 , the count result is obtained after the occurrence of the terminal condition by multiplying the lower count register with a result of applying an exponentiation function to the upper count register.
8. The device of claim 7 , wherein the exponentiation function is arranged to shift a set bit in the prescaler by a number of times that is indicated by the upper count register.
9. The device of claim 8 , wherein the count result is an approximation of the total number of signaled events.
10. The device of claim 9 , wherein count result has an absolute error that is determined in accordance with the function: absolute error function can be described as (2^prescaler)/2, where prescaler is the value of the upper count register.
11. A prescaling system, comprising
a processor that is arranged to monitor a process by evaluating signaled events generated by the process;
a prescaling unit that includes a programmable divider that is arranged to divide an event clock that includes indications of the signaled events to generate a prescaled clock in response to a prescaling value; and
a counter having a register that includes a lower count register and an upper count register for generating a count result, wherein the counter is arranged to increment the lower count register in response to the prescaled clock, wherein the counter arranged to increment the upper count register in response to a terminal condition in the lower count register; and wherein the prescaling value is generated in response to the upper count register.
12. The system of claim 11 , wherein the prescaling value is generated in response to an exponentiation function that uses the upper count register as input to the exponentiation function.
13. The system of claim 12 , wherein the terminal condition is a rollover condition.
14. The system of claim 11 , wherein the processor is arranged to determine the count result by multiplying the lower count register with a result of applying an exponentiation function to the upper count register.
15. The system of claim 14 , wherein the count result is an approximation of the total number of signaled events having an absolute error that is determined in accordance with the function: absolute error function can be described as (2^prescaler)/2, where “prescaler” is the value of the upper count register.
16. A method, comprising
receiving an event clock that includes indications of signaled events;
dividing the event clock in response to a prescaling value to generate a prescaled clock;
incrementing a lower count register in response to the prescaled clock;
incrementing an upper count register in response to a terminal condition in the lower count register; and
generating the prescaling value in response to the upper count register.
17. The method of claim 16 , wherein the prescaled value is generated in response to an exponentiation function that uses the upper count register as input to the exponentiation function.
18. The method of claim 17 , wherein the terminal condition is a rollover condition.
19. The method of claim 16 , comprising generating a count result after an occurrence of the terminal condition by multiplying the lower count register with a result of applying an exponentiation function to the upper count register.
20. The method of claim 19 , wherein the count result is an approximation of the total number of the signaled events having an absolute error that is determined in accordance with the function: absolute error function can be described as (2^prescaler)/2, where “prescaler” is the value of the upper count register.