Dual-Port Memory and a Method Thereof
A dual-port memory is provided. The dual-port memory includes a first single-port memory and a second single-port memory. The first single-port memory is configured to store data in an even address of the dual-port memory. The second single-port memory is configured to store data in an odd address of the dual-port memory. The dual-port memory simultaneously performs a read operation to read data from the odd address and a write operation to write data into the even address. The dual-port memory simultaneously performs a read operation to read data from the even address and a write operation to write data into the odd address.
1 . A dual-port memory, comprising:
a first single-port memory configured to store data at an even address of the dual-port memory; and
a second single-port memory configured to store data at an odd address of the dual-port memory, wherein
the dual-port memory simultaneously performs a read operation to read data from the odd address and a write operation to write data into the even address, and
the dual-port memory simultaneously performs a read operation to read data from the even address and a write operation to write data into the odd address.
2 . The dual-port memory of claim 1 , further comprising:
a first pair of multiplexers comprising a first multiplexer and a second multiplexer and configured to provide a chip enable signal to at least one of the first single-port memory and the second single-port memory by selecting an external read operation enable signal and an external write operation enable signal,
wherein the first multiplexer is coupled to the first single-port memory, and the second multiplexer is coupled to the second single-port memory.
3 . The dual-port memory of claim 2 , further comprising:
a second pair of multiplexers comprising a third multiplexer and a fourth multiplexer and configured to provide a write enable signal to at least one of the first single-port memory and the second single-port memory by selecting the external write operation enable signal and a signal mask,
wherein the third multiplexer is coupled to the first single-port memory, and the fourth multiplexer is coupled to the second single-port memory.
4 . The dual-port memory of claim 3 , further comprising:
a third pair of multiplexers comprising a fifth multiplexer and a sixth multiplexer and configured to provide a read/write address to at least one of the first single-port memory and the second single-port memory based on an external read address and an external write address,
wherein the fifth multiplexer is coupled to the first single-port memory, and the sixth multiplexer is coupled to the second single-port memory.
5 . The dual-port memory of claim 4 , wherein the third pair of multiplexers provides a read address to at least one of the first single-port memory and the second single-port memory based on a quotient of the external read address divided by two; and
the third pair of multiplexers provides a write address to at least one of the first single-port memory and the second single-port memory based on a quotient of the external write address divided by two.
6 . The dual-port memory of claim 4 , wherein a pair of selection signals in each pair of said multiplexers are opposite to each other when the read operation and the write operation are performed simultaneously.
7 . The dual-port memory of claim 4 , wherein a selection signal of each multiplexer is determined by a parity of the external read address and the external write address.
8 . The dual-port memory of claim 7 , wherein the selection signal of each multiplexer is determined based on a least significant bit (LSB) of the external read address and a least significant bit (LSB) of the external write address.
9 . The dual-port memory of claim 4 , further comprising:
an output multiplexer configured to output data read from the first single-port memory or the second single-port memory.
10 . The dual-port memory of claim 9 , further comprising:
a flip-flop configured to provide a selection signal to the output multiplexer, wherein the selection signal is determined by a parity of the external read address and the external write address.
11 . A method, comprising:
storing data at an even address of a dual-port memory into a first single-port memory;
storing data at an odd address of said dual-port memory into a second single-port memory;
enabling the first single-port memory and the second single-port memory by a first pair of multiplexers;
providing a write enable signal to a selected single-port memory of the first single-port memory and the second single-port memory by a second pair of multiplexers to enable the selected single-port memory to perform a write operation; and
providing a write address to the selected single-port memory by a third pair of multiplexers to enable the selected single-port memory to write data into the write address.
12 . The method of claim 11 , further comprising:
providing a read address to the other single-port memory of the first single-port memory and the second single-port memory by the third pair of multiplexers to enable the other single-port memory to perform a read operation and read data from the read address.
13 . The method of claim 12 , wherein the first pair of multiplexers comprise a first multiplexer and a second multiplexer, and are configured to provide a chip enable signal to the first single-port memory and the second single-port memory by selecting an external read operation enable signal and an external write operation enable signal to enable the first single-port memory and the second single-port memory,
wherein the first multiplexer is coupled to the first single-port memory, and the second multiplexer is coupled to the second single-port memory.
14 . The method of claim 13 , wherein the second pair of multiplexers comprise a third multiplexer and a fourth multiplexer, and are configured to provide the write enable signal to the selected single-port memory by selecting the external write operation enable signal and a signal mask,
wherein the third multiplexer is coupled to the first single-port memory, and the fourth multiplexer is coupled to the second single-port memory.
15 . The method of claim 14 , wherein the third pair of multiplexers comprise a fifth multiplexer and a sixth multiplexer, and are configured to provide the write address to the selected single-port memory and provide the read address to the other single-port memory based on an external read address and an external write address.
16 . The method of claim 15 , wherein the third pair of multiplexers provide the read address to the other single-port memory based on a quotient of the external read address divided by two, and
the third pair of multiplexers provide the write address to the selected single-port memory based on a quotient of the external write address divided by two.
17 . The method of claim 15 , wherein a pair of selection signals in each pair of the multiplexers are opposite to each other when the read operation and the write operation are performed simultaneously.
18 . The method of claim 15 , wherein a selection signal of each multiplexer is determined by a parity of the external read address and the external write address.
19 . The method of claim 18 , wherein the selection signal of each multiplexer is determined based on a least significant bit (LSB) of the external read address and a least significant bit (LSB) of said external write address.
20 . The method of claim 15 , further comprising:
outputting data read from the other single-port memory by an output multiplexer.
21 . The method of claim 20 , further comprising:
providing a selection signal to the output multiplexer by a flip-flop, wherein the selection signal is determined by a parity of the external read address and the external write address.