Semiconductor device with buffer layer
View Patent ↗A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
1. A method comprising:
forming a second semiconductor layer on a first semiconductor layer, wherein the first semiconductor layer has a first concentration of a first dopant type;
forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer has a second concentration of the first dopant type that is less than the first concentration and wherein the second semiconductor layer has a graded concentration of the first dopant type that is substantially equal to the second concentration proximate the third semiconductor layer and greater than the second concentration proximate the first semiconductor layer, wherein the width of second semiconductor layer is between ten and forty five percent of the width of the third semiconductor layer, wherein the doping profile of the second semiconductor layer has a concentration approximately equal to the doping concentration in the third semiconductor layer proximate the third semiconductor layer, and wherein the doping concentration of the second semiconductor layer is between five and twenty times greater than the doping concentration of the third semiconductor layer proximate the first semiconductor layer;
forming a guard region in the third semiconductor layer opposite the second semiconductor layer, wherein the guard region has a first concentration of a second dopant type such that the width and smooth graded doping profile of the second semiconductor layer reduces an electric field proximate the guard region; and
depositing a metal layer on the third semiconductor opposite the second semiconductor layer and a portion of the guard region, wherein the metal layer forms a Schottky junction with the third semiconductor layer.
2. The method according to claim 1 , wherein:
forming the second semiconductor layer comprises epitaxially depositing a semiconductor starting with a peak concentration of approximately 0.5E15 cm −3 to 0.5E17 cm −3 and ending with a concentration of approximately 0.5E14 cm −3 to 0.5E16 cm −3 ; and
forming the third semiconductor layer comprises epitaxially depositing the semiconductor with a concentration of approximately 0.5E14 cm −3 to 0.5E1.6 cm −3 .
3. The method according to claim 1 , further comprising forming a termination region oxide between a portion of the third semiconductor layer and the metal layer adjacent the Schottky junction and overlaying a portion of the guard region.
4. The method according to claim 1 , wherein depositing the metal layer comprises:
depositing one or more metals selected from a first group consisting of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), nickel (Ni), cobalt (Co) and molybdenum (Mo) on the third semiconductor layer; and
depositing one or more metals selected from a second group consisting of nickel-gold (Ni/Au), nickel-silver (Ni/Ag), aluminum (Al), copper (Cu), titanium nitride (TiN), titanium (Ti), titanium tungsten (TiW) on the one or more metal selected from the first group.
5. A method comprising:
forming a second semiconductor layer on a first semiconductor layer, wherein the first semiconductor layer has a first concentration of a first dopant type;
forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer has a second concentration of the first dopant type that is less than the first concentration, wherein the second semiconductor layer has a graded concentration of the first dopant type that is substantially equal to the second concentration proximate the third semiconductor layer and greater than the second concentration proximate the first semiconductor layer, and wherein the width of second semiconductor layer is between ten and fort five percent of the width of the third semiconductor layer;
forming a guard region in the third semiconductor layer opposite the second semiconductor layer, wherein the guard region has a first concentration of a second dopant type; and
depositing a metal layer on the third semiconductor opposite the second semiconductor layer and a portion of the guard region, wherein the metal layer forms a Schottky junction with the third semiconductor layer.
6. The method according to claim 5 , wherein:
forming the second semiconductor layer comprises epitaxially depositing a semiconductor starting with a peak concentration of approximately 0.5E15 cm −3 to 0.5E17 cm −3 and ending with a concentration of approximately 0.5E14 cm −3 to 0.5E16 cm −3 ; and
forming the third semiconductor layer comprises epitaxially depositing the semiconductor with a concentration of approximately 0.5E14 cm −3 to 0.5E16 cm −3 .
7. The method according to claim 6 , wherein:
the dopant of the first type comprises phosphorous or arsenic; and
the dopant of the second type comprises boron.
8. The method according to claim 5 , further comprising forming a termination region oxide between a portion of the third semiconductor layer and the metal layer adjacent the Schottky junction and overlaying a portion of the guard region.
9. The method according to claim 5 , wherein depositing the metal layer comprises:
depositing one or more metals selected from a first group consisting of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), nickel (Ni), cobalt (Co) and molybdenum (Mo) on the third semiconductor layer; and
depositing one or more metals selected from a second group consisting of nickel-gold (Ni/Au), nickel-silver (Ni/Ag), aluminum (Al), copper (Cu), titanium nitride (TiN), titanium (Ti), titanium tungsten (TiW) on the one or more metal selected from the first group.
10. The method according to claim 5 , wherein the graded concentration of the second semiconductor layer reduces the electric field proximate the Schottky junction.
11. The method according to claim 5 , wherein the graded concentration of the second semiconductor layer reduces a double-injection phenomenon proximately the Schottky junction.
12. A method comprising:
forming a depletion junction;
forming a peripheral region adjacent the depletion junction; and
forming a buffer layer proximate an interface between the depletion junction and the peripheral region, wherein the buffer layer reduces localization of avalanche breakdown proximate the interface and wherein the width and a smooth graded doping profile of the buffer layer reduces an electric field proximate the peripheral region adjacent the depletion junction.
13. The method according to claim 12 , wherein the depletion junction comprises a junction between a p-type semiconductor and an n-type semiconductor.
14. The method according to claim 12 , wherein the depletion junction comprises a junction between a semiconductor and a metal.
15. The method according to claim 12 , wherein the buffer layer comprises a substantial linear doping profile.
16. The method according to claim 12 , wherein the smooth graded doping profile of the buffer layer reduces localization of avalanche breakdown proximate the interface.
17. The method according to claim 12 , wherein the semiconductor device comprises a diode.
18. The method according to claim 12 , wherein the semiconductor device comprises a Schottky diode.
19. The method according to claim 12 , wherein the semiconductor device comprises a rectifier.