IP Library Granted Patent US 8,745,276
Granted Patent B2
US 8,745,276 · App. 13/628,187 · Granted Jun 3, 2014

Use of free pages in handling of page faults

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Quick Facts
Patent No.
US 8,745,276
App. No.
13/628,187
Granted
Jun 3, 2014
Kind
B2
Abstract

A method for data transfer includes receiving in an input/output (I/O) operation data to be written to a specified virtual address in a host memory. Upon receiving the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. Responsively to detecting that the first page is swapped out, the received data are written to a second, free page in the host memory, and the specified virtual address is remapped to the free page.

Claims (19)

1. A method for data transfer, comprising:

receiving in an input/output (I/O) operation by an I/O device data to be written to a specified virtual address in a host memory belonging to a host processor having a memory management unit (MMU) associated with the host memory, wherein the host processor is configured to maintain address translation tables, indicating a correspondence between virtual addresses used by applications running on the host processor and physical addresses in the host memory, and

wherein the I/O device is coupled to receive the address translation tables from the host processor, and is configured to receive data to be written to specified virtual addresses in I/O operations and to refer to the address translation tables in order to write the received data directly to corresponding physical addresses in the host memory;

detecting, using the address translation tables in the I/O device, upon receiving the data, that a first page that contains the specified virtual address is swapped out of the host memory; and

responsively to detecting that the first page is swapped out, writing the received data from the I/O device to a second, free page in the host memory and remapping the specified virtual address to the free page.

2. The method according to claim 1 , wherein the I/O device comprises a network interface controller, and wherein receiving the data comprises receiving, in the network interface controller, a data packet containing the data transmitted over a network.

3. The method according to claim 2 , wherein writing the received data comprises writing first data from a first data packet to the free page, and wherein the method comprises, after remapping the specified virtual address to the free page, receiving a second data packet containing second data from the network, and writing the second data to the remapped page following the first data.

4. The method according to claim 1 , wherein the I/O operation is directed to a virtual machine running a guest operating system supported by a hypervisor, and wherein remapping the specified virtual address comprises remapping, by the hypervisor, a virtual memory page to a physical memory page, which is mapped to a machine memory page in a host operating system.

5. The method according to claim 1 , wherein writing the received data comprises receiving an indication from a user application that contents of the first page are no longer needed, and overwriting the second page with the received data responsively to the indication.

6. The method according to claim 5 , wherein receiving the indication comprises receiving a work item, posted by the user application, indicating that the free page should be allocated for writing the received data.

7. Data processing apparatus, comprising:

a host processor having a host memory and a memory management unit (MMU) associated with the host memory, wherein the host processor is configured to maintain address translation tables, indicating a correspondence between virtual addresses used by applications running on the host processor and physical addresses in the host memory; and

an input/output (I/O) device, which is coupled to receive the address translation tables from the host processor, and is configured to receive data to be written to specified virtual addresses in I/O operations and to refer to the address translation tables in order to write the received data directly to corresponding physical addresses in the host memory,

wherein the I/O device is configured, upon receiving in an I/O operation data to be written to a specified virtual address in the host memory, and detecting, upon receiving the data, according to the address translation tables, that a first page that contains the specified virtual address is swapped out of the host memory, to write the received data to a second, free page in the host memory, while causing the MMU to remap the specified virtual address to the free page.

8. The apparatus according to claim 7 , wherein the I/O device comprises a network interface controller (NIC), which is configured to receive one or more data packets containing the data transmitted over a network.

9. The apparatus according to claim 8 , wherein the NIC is configured to write first data from a first data packet to the free page, and after remapping of the specified virtual address to the free page, to receive a second data packet containing second data from the network, and to write the second data to the remapped page following the first data.

10. The apparatus according to claim 7 , wherein the I/O operation is directed to a virtual machine running a guest operating system supported by a hypervisor on the host processor, and wherein the hypervisor is configured to remap a virtual memory page containing the specified virtual address to a physical memory page, which is mapped by the MMU to a machine memory page.

11. The apparatus according to claim 7 , wherein the I/O device is configured to overwrite the second page with the received data after receiving an indication from a user application that contents of the first page are no longer needed.

12. The apparatus according to claim 11 , wherein the indication comprises a work item, posted by the user application, indicating that the free page should be allocated for writing the received data.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 37900/0720 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 046542/0792 →
PATENT SECURITY AGREEMENT Recorded Feb 24, 2016
From: MELLANOX TECHNOLOGIES, LTD.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 037900/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2012
From: BLOCH, NOAM; RAINDEL, SHACHAR; ERAN, HAGGAI; LISS, LIRAN
To: MELLANOX TECHNOLOGIES LTD.
Reel/Frame 029035/0229 →