Low-voltage, high-speed, current-mode latch with inductor tail and common-mode feedback for amplitude and current control
View Patent ↗Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively.
1. An apparatus, comprising:
a first transistor pair that accepts clock inputs;
a second transistor pair that receives data inputs and sends data outputs to a logic gate, wherein the second transistor pair is stacked upon the first transistor pair; and
a tail inductor coupled to the first transistor pair, wherein the tail inductor stabilizes current flow during clock transitions at high frequency.
2. The apparatus of claim 1 , further comprising:
a circuit configured to generate a clock waveform that has a defined frequency for a high-speed serial data stream, wherein the first transistor pair and the second transistor pair are utilized to phase align the clock waveform to transitions in the high-speed serial data stream based on employing a phase locked loop circuit.
3. The apparatus of claim 1 , wherein the tail inductor suppresses high frequency common mode bounce induced by the clock transitions in independent common emitter branches.
4. The apparatus of claim 1 , further comprising a common mode feedback loop.
5. The apparatus of claim 4 , wherein the common mode feedback loop maintains a constant average current.
6. The apparatus of claim 4 , wherein the common mode feedback loop is shared between a plurality of circuits.
7. The apparatus of claim 4 , wherein the tail inductor is shared between a plurality of circuits
8. The apparatus of claim 1 , wherein an operating voltage is under 2.0 volts.
9. The apparatus of claim 1 , wherein the first and the second transistor pairs are at least one of heterojunction bipolar transistors, bipolar transistors or field effect transistors.
10. A low-voltage circuit, comprising:
a first transistor pair that accepts periodic inputs;
a second transistor pair that receives data inputs and sends data outputs to a logic gate, wherein the second transistor pair is stacked upon the first transistor pair;
a common mode feedback loop that maintains a constant average current; and
a tail inductor coupled to the first transistor pair, wherein the tail inductor suppresses high frequency common mode bounce induced by clock transitions in independent common emitter branches.
11. The low-voltage circuit of claim 10 , wherein the common mode feedback loop is shared between a plurality of low-voltage circuits.
12. The low-voltage circuit of claim 10 , further comprising a control node that provides a reference voltage.
13. The low-voltage circuit of claim 10 , wherein an operating voltage of the low-voltage circuit is under 2.0 volts.
14. The low-voltage circuit of claim 10 , wherein the tail inductor is coupled to a plurality of low-voltage circuits.
15. The low-voltage circuit of claim 10 , wherein the tail inductor stabilizes current flow during high frequency clock transitions and the common mode feedback loop maintains a constant average current.
16. The low-voltage circuit of claim 10 , wherein the first and the second transistor pairs are at least one of heterojunction bipolar transistors, bipolar transistors or field effect transistors.
17. The low-voltage circuit of claim 10 , further comprising:
a phase locked loop circuit that phase aligns a clock waveform generated for a high-speed serial data stream that is received by the second transistor pair, to transitions in the high-speed serial data stream.
18. A method for stabilizing current in low-voltage differential circuits comprising:
receiving clock inputs;
receiving data inputs and outputting data outputs to a logic gate;
maintaining a constant average current by a common mode feedback loop; and
suppressing common mode bounce induced by high frequency clock transitions using a tail inductor.
19. The method of claim 18 , wherein the receiving the clock inputs and the data inputs is facilitated respectively by a first transistor pair and a second transistor pair.
20. The method of claim 18 , wherein the suppressing common mode bounce further comprises suppressing common mode bounce in independent common emitter branches.