Circuit and power amplifier
A cascode circuit includes a first transistor and a second transistor. The first transistor and the second transistor are connected to make a cascode. In addition, the circuit has a block capacitance which is connected between a control terminal of the second transistor and a source terminal of the first transistor. In addition, the circuit has a feedback element which is connected between a drain terminal of the second transistor and a control terminal of the first transistor.
1. A circuit comprising the following features:
a signal input;
a signal output;
a first transistor;
a second transistor;
wherein the first transistor and the second transistor are connected to make a cascode;
wherein the cascode is connected between the signal input and the signal output of the circuit;
a block capacitor which is connected between a control terminal of the second transistor and a source terminal of the first transistor; and
a feedback element, which is connected between a drain terminal of the second transistor and a control terminal of the first transistor;
wherein the feedback element comprises a reconfigurable feedback network.
2. A circuit comprising the following features:
a signal input;
a signal output;
a first transistor;
a second transistor;
wherein the first transistor and the second transistor are connected to make a cascode;
wherein the cascode is connected between the signal input and the signal output of the circuit;
a block capacitor which is connected between a control terminal of the second transistor and a source terminal of the first transistor; and
a feedback element, which is connected between a drain terminal of the second transistor and a control terminal of the first transistor;
wherein the feedback element comprises a feedback inductor connected between the drain terminal of the second transistor and the control terminal of the first transistor.
3. The circuit according to claim 2 , wherein the feedback element further comprises a feedback resistance element connected between the drain terminal of the second transistor and the control terminal of the first transistor.
4. The circuit according to claim 2 , wherein the feedback element further comprises a feedback capacitor connected between the drain terminal of the second transistor and the control terminal of the first transistor.
5. The circuit according to claim 4 , wherein a capacitance of the feedback capacitor is larger than a capacitance between the drain terminal of the second transistor and the control terminal of the second transistor.
6. The circuit according to claim 1 ,
wherein the reconfigurable feedback network comprises a plurality of series switches and a plurality of impedance elements; and
wherein the series switches and the impedance elements are connected between the drain terminal of the second transistor and the control terminal of the first transistor in such a manner that one impedance element from the plurality of impedance elements is connected to a series switch from the plurality of series switches.
7. The circuit according to claim 1 ,
wherein the reconfigurable feedback network comprises a plurality of parallel switches and a plurality of impedance elements;
wherein the impedance elements are connected between the drain terminal of the second transistor and the control terminal of the first transistor; and
wherein the parallel switches are connected between the impedance elements and a supply potential terminal of the circuit in such a manner that one impedance element from the plurality of impedance elements is connected to a parallel switch from the plurality of parallel switches.
8. The circuit according to claim 1 ,
wherein the reconfigurable feedback network comprises a feedback capacitor and a plurality of switchable feedback resistance elements which are connected to each other in parallel; and
wherein the feedback capacitor and the plurality of switchable feedback resistance elements are connected between the drain terminal of the second transistor and the control terminal of the first transistor in such a manner that the feedback capacitor is coupled to the plurality of switchable feedback resistance elements.
9. The circuit according to claim 1 , wherein a drain terminal of the first transistor is connected to a source terminal of the second transistor in order to form the cascode.
10. The circuit according to claim 1 , wherein the source terminal of the first transistor forms a signal input of the cascode, and the drain terminal of the second transistor forms the signal output of the circuit.
11. The circuit according to claim 1 , further comprising a third transistor and a fourth transistor;
wherein the third transistor and the fourth transistor are connected to make a further cascode; and
wherein the cascode and the further cascode are stacked in such a manner that the source terminal of the first transistor is connected to a drain terminal of the fourth transistor.
12. The circuit according to claim 1 , wherein the source terminal of the first transistor forms a high-frequency signal input of the cascode.
13. A circuit arrangement comprising the following features:
a circuit comprising the following features:
a signal input;
a signal output;
a first transistor;
a second transistor;
wherein the first transistor and the second transistor are connected to make a cascode;
wherein the cascode is connected between the signal input and the signal output of the circuit;
a block capacitor which is connected between a control terminal of the second transistor and a source terminal of the first transistor; and
a feedback element, which is connected between a drain terminal of the second transistor and a control terminal of the first transistor; and
a further circuit, which is connected between a signal input of the cascode and an input terminal of the circuit arrangement.
14. The circuit arrangement according to claim 13 , wherein the further circuit is connected to a ground terminal.
15. A circuit comprising the following features:
a signal input;
a signal output;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
wherein the first transistor and the second transistor are connected to make a cascode;
wherein the third transistor and the fourth transistor are connected to make a further cascode; and
wherein the cascode and the further cascode are stacked in such a manner that a source terminal of the first transistor is connected to a drain terminal of the fourth transistor;
a block capacitor which is connected between a control terminal of the second transistor and the source terminal of the first transistor;
a feedback capacitor which is connected between a drain terminal of the second transistor and a control terminal of the first transistor; and
wherein a capacitance of the feedback capacitor is larger than a capacitance between the drain terminal of the second transistor and the control terminal of the second transistor;
wherein the drain terminal of the second transistor forms the signal output of the circuit;
wherein a control terminal of the third transistor forms the signal input of the circuit.
16. A power amplifier comprising a circuit arrangement, the circuit arrangement comprising the following features:
a circuit comprising the following features:
a signal input;
a signal output;
a first transistor;
a second transistor;
wherein the first transistor and the second transistor are connected to make a cascode;
wherein the cascode is connected between the signal input and the signal output of the circuit;
a block capacitor which is connected between a control terminal of the second transistor and a source terminal of the first transistor; and
a feedback element, which is connected between a drain terminal of the second transistor and a control terminal of the first transistor; and
a further circuit, which is connected between a signal input of the cascode and an input terminal of the circuit arrangement.
17. A power amplifier comprising a circuit, the circuit comprising the following features:
a signal input;
a signal output;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
wherein the first transistor and the second transistor are connected to make a cascode;
wherein the third transistor and the fourth transistor are connected to make a further cascode; and
wherein the cascode and the further cascode are stacked in such a manner that a source terminal of the first transistor is connected to a drain terminal of the fourth transistor;
a block capacitor which is connected between a control terminal of the second transistor and the source terminal of the first transistor;
a feedback capacitor which is connected between a drain terminal of the second transistor and a control terminal of the first transistor; and
wherein a capacitance of the feedback capacitor is larger than a capacitance between the drain terminal of the second transistor and the control terminal of the second transistor;
wherein the drain terminal of the second transistor forms the signal output of the circuit;
wherein a control terminal of the third transistor forms the signal input of the circuit.