Phase locked loop with power supply control
View Patent ↗A phase locked loop (PLL) includes a phase frequency detector powered by a first analog supply voltage; a charge pump powered by a second analog supply voltage, different from the first analog supply voltage; a voltage controlled oscillator (VCO) powered by a third analog supply voltage, different from the first and second analog supply voltages, wherein a frequency of the VCO is controlled by a control voltage; and a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, a second circuit node which provides the first analog supply voltage, a third circuit node which provides the second analog supply voltage, and a fourth circuit node which provides the third analog supply voltage, and a current compensator coupled to one of the second, third, or fourth circuit nodes, wherein the current compensator provides a variable current draw based on the control voltage.
1. A phase locked loop (PLL) comprising:
a phase frequency detector powered by a first analog supply voltage;
a charge pump coupled to the phase frequency detector, the charge pump powered by a second analog supply voltage, different from the first analog supply voltage;
a voltage controlled oscillator (VCO) coupled to the charge pump, the VCO powered by a third analog supply voltage, different from the first analog supply voltage and different from the second analog supply voltage, wherein a frequency of the VCO is controlled by a control voltage; and
a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, a second circuit node which provides the first analog supply voltage, a third circuit node which provides the second analog supply voltage, and a fourth circuit node which provides the third analog supply voltage, and a current compensator coupled to one of the second, third, or fourth circuit nodes, wherein the current compensator provides a variable current draw from the one of the second, third, or fourth circuit nodes based on the control voltage.
2. The PLL of claim 1 wherein the first circuit node and the second circuit node are a same circuit node.
3. The PLL of claim 1 , further comprising:
a filtering circuit coupled to each of the second, third, and fourth circuit nodes, wherein each filtering circuit has a different noise cutoff frequency.
4. The PLL of claim 1 , wherein the supply voltage provider comprises:
a first resistor having a first terminal coupled to the second circuit node and a second terminal coupled to the third circuit node;
a second resistor having a first terminal coupled to the third circuit node and a second terminal coupled to the fourth circuit node;
a third resistor having a first terminal coupled to the fourth circuit node and a second terminal coupled to ground; and
a first capacitor having a first terminal coupled to the third circuit node and a second terminal coupled to ground.
5. The PLL of claim 1 , wherein the current compensator is coupled to the fourth circuit node and provides the variable current draw from the fourth circuit node based on the control voltage such that the fourth circuit node remains at a substantially constant predetermined voltage level.
6. The PLL of claim 5 , wherein the current compensator comprises:
a first N-channel transistor having a control electrode coupled to receive the control voltage, a first current electrode, and a second current electrode coupled to ground;
a second N-channel transistor having a control electrode coupled to the first current electrode of the first N-channel transistor, a first current electrode, and a second current electrode coupled to ground;
a first P-channel transistor having a first current electrode coupled to the fourth circuit node which provides the third analog supply voltage, a control electrode coupled to the first current electrode of the second N-channel transistor, and a second current electrode coupled to the first current electrode of the second N-channel transistor; and
a second P-channel transistor having a first current electrode coupled to the fourth circuit node which provides the third analog supply voltage, a control electrode coupled to the first current electrode of the first N-channel transistor, and a second current electrode coupled to the first current electrode of the first N-channel transistor.
7. The PLL of claim 6 , wherein a current through the second N-channel transistor is inversely proportional to a current consumed by the VCO.
8. The PLL of claim 1 , further comprising:
a voltage translation module coupled to receive an input control voltage from the charge pump which has a maximum voltage value of the second analog supply voltage and to provide the control voltage to the VCO, wherein the control voltage is proportional to the input control voltage and has a maximum voltage value of the third analog supply voltage.
9. The PLL of claim 8 , further comprising:
a clock receiver coupled to the phase frequency detector and powered by a logic supply voltage; and
a frequency divider coupled between the VCO and the clock receiver and powered by the logic supply voltage.
10. An integrated circuit comprising the PLL of claim 1 , wherein the fourth analog supply voltage is received at an input pad of the integrated circuit.
11. The PLL of claim 1 , wherein the supply voltage provider is devoid of a bandgap reference generator.
12. A phase locked loop (PLL) comprising:
a phase frequency detector powered by a first analog supply voltage;
a charge pump coupled to the phase frequency detector, the charge pump powered by a second analog supply voltage, different from the first analog supply voltage;
a voltage controlled oscillator (VCO) coupled to the charge pump, the VCO powered by a third analog supply voltage, different from the first analog supply voltage and different from the second analog supply voltage, wherein a frequency of the VCO is controlled by a control voltage; and
a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, the supply voltage provider comprising:
a first resistor having a first terminal coupled to the first circuit node and a second terminal coupled to a second circuit node;
a second resistor having a first terminal coupled to the second circuit node and a second terminal coupled to a third circuit node;
a third resistor having a first terminal coupled to the third circuit node and a second terminal coupled to ground; and
a first capacitor having a first terminal coupled to the third circuit node and a second terminal coupled to ground, wherein the first circuit node provides the first analog supply voltage, the second circuit node provides the second analog supply voltage, and the third circuit node provides the third analog supply voltage.
13. The PLL of claim 12 , further comprising:
a second capacitor having a first terminal coupled to the second circuit node and a second terminal coupled to ground.
14. The PLL of claim 13 , further comprising:
a third capacitor having a first terminal coupled to the first circuit node and a second terminal coupled to ground.
15. The PLL of claim 12 , further comprising:
a current compensator coupled to the third circuit node, wherein the current compensator provides a variable current draw from the third circuit node based on the control voltage.
16. The PLL of claim 12 , further comprising:
a voltage translation module coupled to receive an input control voltage from the charge pump which has a maximum voltage value of the second analog supply voltage and to provide the control voltage to the VCO, wherein the control voltage is proportional to the input control voltage and has a maximum voltage value of the third analog supply voltage.
17. In a phase locked loop (PLL), a method comprising:
providing a first analog supply voltage from a first circuit node of a plurality of series-connected resistors to a phase frequency detector of the PLL;
providing a second analog supply voltage from a second circuit node of the plurality of series-connected resistors to a charge pump of the PLL;
providing a third analog supply voltage from a third circuit node of the plurality of series-connected resistors to a VCO of the PLL, wherein each of the first, second, and third analog supply voltages are different;
providing an input control voltage to the VCO to control a frequency of the VCO, wherein the input control voltage is provided based on an output control voltage of the charge pump; and
drawing a variable current from the third circuit node in response to the input control voltage such that the third analog supply voltage remains at a substantially constant predetermined voltage level.
18. The method of claim 17 , further comprising:
filtering noise at the first circuit node using a first noise cutoff frequency;
filtering noise at the second circuit node using a second noise cutoff frequency; and
filtering noise at the third circuit node using a third noise cutoff frequency, wherein the first, second, and noise cutoff frequencies are different from each other.
19. The method of claim 17 , further comprising:
receiving an external analog supply voltage at the first circuit node of the plurality of series-connected resistors.
20. The method of claim 17 , wherein the drawing a variable current from the third circuit node in response to the input control voltage is characterized in that the variable current is inversely proportional to a current consumed by the VCO.