Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance
View Patent ↗A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.
1. A method of operating a processor, comprising:
translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number, associated with a first multi-bit translation lookaside buffer way and a first multi-bit translation lookaside buffer index, in the translation lookaside buffer;
translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number, associated with a second multi-bit translation lookaside buffer way and a second multi-bit translation lookaside buffer index, in the translation lookaside buffer; and
determining that the first and second virtual addresses point to a same physical address in memory and reference same data by determining the first multi-bit translation lookaside buffer way is equal to the second multi-bit translation lookaside buffer way and the first multi-bit translation lookaside buffer index is equal to the second multi-bit translation lookaside buffer index.
2. The method of claim 1 , wherein the first entry number is associated with a first address in a first content-addressable memory that is included in a store buffer and the second virtual address is associated with a load operation, and wherein store data in the store buffer is forwarded to the load operation, and where the first and second entry numbers are associated with at least a 2-bit translation lookaside buffer way and at least a 4-bit translation lookaside buffer index.
3. The method of claim 1 , wherein the first entry number is associated with a first address that is included in a first tag array of a cache and the second virtual address is associated with a load operation, and wherein store data in a data array of the cache is fetched in response to the load operation.
4. The method of claim 1 , wherein replacement of an entry in the translation lookaside buffer includes searching all entries in the translation lookaside buffer for aliasing and invalidating any aliased entries in the translation lookaside buffer.
5. The method of claim 2 , wherein replacement of an entry in the translation lookaside buffer is delayed until the entry to be replaced does not exist in the store buffer.
6. The method of claim 2 , wherein invalidation of an entry in the translation lookaside buffer is delayed until the entry to be invalidated does not exist in the store buffer.
7. The method of claim 3 , wherein replacement of an entry in the translation lookaside buffer invalidates all matched entries in the tag array of the cache.
8. The method of claim 3 , wherein invalidation of an entry in the translation lookaside buffer invalidates all matched entries in the tag array of the cache.
9. The method of claim 3 , wherein the cache includes a second tag array with physical addresses for snooping and translated physical addresses that are not in the translation lookaside buffer.
10. The method of claim 9 , wherein an aliased entry in the cache is restored to a new entry in the translation lookaside buffer by a hit in the second tag array.
11. A data processing system, comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to translate, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number, associated with a first multi-bit translation lookaside buffer way and a first multi-bit translation lookaside buffer index, in the translation lookaside buffer, translate, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number, associated with a second multi-bit translation lookaside buffer way and a second multi-bit translation lookaside buffer index, in the translation lookaside buffer and, determine that the first and second virtual addresses point to the same physical address in memory and reference the same data via a determination the first multi-bit translation lookaside buffer way is equal to the second multi-bit translation lookaside buffer way and the first multi-bit translation lookaside buffer index is equal to the second multi-bit translation lookaside buffer index.
12. The data processing system of claim 11 , wherein the first entry number is associated with a first address in a first content-addressable memory that is included in a store buffer and the second virtual address is associated with a load operation, and wherein store data in the store buffer is forwarded to the load operation.
13. The data processing system of claim 11 , wherein the first entry number is associated with a first address that is included in a first tag array of a cache and the second virtual address is associated with a load operation, and wherein store data in a data array of the cache is fetched in response to the load operation.
14. The data processing system of claim 11 , wherein replacement of an entry in the translation lookaside buffer includes searching all entries in the translation lookaside buffer for aliasing and invalidating any aliased entries in the translation lookaside buffer.
15. The data processing system of claim 12 , wherein replacement of an entry in the translation lookaside buffer is delayed until the entry to be replaced does not exist in the store buffer.
16. The data processing system of claim 12 , wherein invalidation of an entry in the translation lookaside buffer is delayed until the entry to be invalidated does not exist in the store buffer.
17. The data processing system of claim 13 , wherein replacement of an entry in the translation lookaside buffer invalidates all matched entries in the tag array of the cache.
18. The data processing system of claim 13 , wherein invalidation of an entry in the translation lookaside buffer invalidates all matched entries in the tag array of the cache.
19. The data processing system of claim 13 , wherein the cache includes a second tag array with physical addresses for snooping and translated physical addresses that are not in the translation lookaside buffer.
20. The data processing system of claim 19 , wherein an aliased entry in the cache is restored to a new entry in the translation lookaside buffer by a hit in the second tag array.
21. A processor, comprising:
a cache memory; and
a processor core coupled to the cache memory, wherein the processor core is configured to translate a first virtual address into a first physical address through a first entry number, associated with a first multi-bit translation lookaside buffer way and a first multi-bit translation lookaside buffer index, in a translation lookaside buffer, translate a second virtual address into a second physical address through a second entry number, associated with a second multi-bit translation lookaside buffer way and a second multi-bit translation lookaside buffer index, in the translation lookaside buffer, and in response to the first entry number being the same as the second entry number as determined by the first multi-bit translation lookaside buffer way being equal to the second multi-bit translation lookaside buffer way and the first multi-bit translation lookaside buffer index being equal to the second multi-bit translation lookaside buffer index, provide data to a load operation associated with the second virtual address.