IP Library Granted Patent US 8,912,670
Granted Patent B2
US 8,912,670 · App. 13/631,205 · Granted Dec 16, 2014

Bumpless build-up layer package including an integrated heat spreader

Inventors: Weng Hong Teh (Phoenix, AZ); Deepak Kulkarni (Chandler, AZ); Chia-Pin Chiu (Tempe, AZ); Tannaz Harirchian (Chandler, AZ); John S. Guzek (Chandler, AZ)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,912,670
App. No.
13/631,205
Granted
Dec 16, 2014
Kind
B2
Abstract

An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Claims (21)

1. A die package comprising:

a microelectronic die having an upper die surface, a lower die surface parallel to the upper die surface, and a die side, the microelectronic die including an active region and an inactive region;

a heat spreader having an upper heat spreader surface, a lower heat spreader surface parallel to the upper heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the lower surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region of the microelectronic die;

an encapsulation material encapsulating the die side and the heat spreader side and upper heat spreader surface, the encapsulation material including an upper surface substantially parallel to the upper die surface and a lower surface substantially parallel to the lower die surface, wherein the encapsulation material defines a lower encapsulation material opening in the lower surface with the lower die surface exposed through the lower encapsulation material opening;

a plurality of build-up layers disposed on the upper surface of the encapsulation material; and

a plurality of conductive traces disposed on the build-up layers and in electrical communication with the active region.

2. The die package of claim 1 , wherein the heat spreader defines a heat spreader opening in the lower surface with the lower die surface exposed through the heat spreader opening, wherein a thermal interface material is disposed between, and in thermal communication with, the upper heat spreader surface and the lower die surface.

3. The die package of claim 1 , wherein the heat spreader extends over the lower die surface, with thermal interface material extending between the lower die surface and the upper heat spreader surface.

4. The die package of claim 1 , wherein at least one thermal conductor is coupled in thermal communication to the upper heat spreader surface and extends through the encapsulation material, parallel the die side, and is coupled in thermal communication with a conductive trace of the plurality of conductive traces, the conductive trace being coupled in thermal communication with the die upper surface.

5. The die package of claim 4 , wherein a grid of thermal conductors is disposed between the conductive trace and the die upper surface, the grid interlaced around contacts of the die and coupled in thermal communication with the at least one thermal conductor.

6. The die package of claim 5 , wherein a second die is disposed between the microelectronic die and the heat spreader, and a second grid is disposed between the microelectronic die and the second die, the second grid interlaced around contacts between the microelectronic die and the second die and coupled in thermal communication with the at least one thermal conductor.

7. The die package of claim 6 , wherein a through via connection extends through the microelectronic die from the die upper surface to the microelectronic die, electrically connecting the plurality of traces to the second die.

8. A system, comprising:

a microelectronic die having an upper die surface, a lower die surface parallel to the upper die surface, and a die side, the microelectronic die including an active region and an inactive region;

a heat spreader having an upper heat spreader surface, a lower heat spreader surface parallel to the upper heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the lower surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region;

an encapsulation material encapsulating the die side and the heat spreader side and upper heat spreader surface, the encapsulation material including an upper surface substantially parallel to the upper die surface and a lower surface substantially parallel to the lower die surface, wherein the encapsulation material defines a lower encapsulation material opening in the lower surface with the lower die surface exposed through the lower encapsulation material opening, wherein the heat spreader defines a heat spreader opening in the lower surface with the lower die surface exposed through the lower encapsulation material opening, wherein at least one electrical interconnect extends through the heat spreader opening and is coupled to through vias of the microelectronic die along the lower die surface, the electrical interconnects coupling a second die to the microelectronic die;

a plurality of build-up layers disposed on the upper surface of the encapsulation material; and

a plurality of conductive traces disposed on the build-up layers and in electrical communication with the active region; and

dynamic random-access memory coupled to the microelectronic die.

9. The system of claim 8 , wherein the microelectronic die is a processor, and wherein the second die is selected from a data storage device, a digital signal processor, a micro controller, an application specific integrated circuit, and a processor.

10. The system of claim 8 , wherein the system is disposed in one of a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2012
From: HONG TEH, WENG; KULKARNI, DEEPAK; CHIU, CHIA-PIN; HARIRCHIAN, TANNAZ; GUZEK, JOHN S
To: INTEL CORPORATION
Reel/Frame 029309/0749 →
Continuity (1)
Related Publication 20140091445A1 · Apr 3, 2014