Superjunction LDMOS and manufacturing method of the same
View Patent ↗A superjunction LDMOS and its manufacturing method are disclosed. The superjunction LDMOS includes a diffused well in which a superjunction structure is formed; the superjunction structure has a depth less than the depth of the diffused well. The manufacturing method includes: provide a semiconductor substrate; form a diffused well in the semiconductor substrate by photolithography and high temperature diffusion; form an STI layer above the diffused well; form a superjunction structure in the diffused well by ion implantation, wherein the superjunction structure has a depth less than the depth of the diffused well; and form the other components of the superjunction LDMOS by subsequent conventional CMOS processes. The method is compatible with conventional CMOS processes and do not require high-cost and complicated special processes.
1. A superjunction LDMOS, comprising:
a drain drift region, wherein the drain drift region comprises a diffused well; and
a superjunction structure, the superjunction structure being formed in an upper part of the diffused well and having a depth less than a depth of the diffused well, wherein a depth to width ratio of the superjunction structure is smaller than 3.
2. The superjunction LDMOS according to claim 1 , wherein the depth of the diffused well is greater than 5 μm.
3. The superjunction LDMOS according to claim 1 , wherein a breakdown voltage of the superjunction LDMOS is greater than 700V.
4. A method of manufacturing the superjunction LDMOS according to claim 1 , comprising the following steps:
providing a semiconductor substrate;
forming a diffused well in the semiconductor substrate by photolithography and high temperature diffusion processes;
forming a shallow trench isolation layer above the diffused well; and
forming a superjunction structure in the diffused well by ion implantation,
wherein the superjunction structure has a depth less than a depth of the diffused well, wherein a depth to width ratio of the superjunction structure is smaller than 3.
5. The method according to claim 4 , wherein the ion implantation process adopts an ion implantation concentration of 1E12/cm 2 to 1E13/cm 2 .
6. The method according to claim 4 , wherein the depth of the diffused well is greater than 5 μm.