Printed dopant layers
View Patent ↗A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
1. A method for making a MOS transistor, comprising:
a) forming a plurality of semiconductor islands by printing or coating a semiconductor ink on an electrically functional substrate;
b) printing a dielectric layer containing a dopant on or over the plurality of semiconductor islands; and
c) annealing the dielectric layer, the semiconductor islands and the substrate sufficiently to diffuse the dopant into the plurality of semiconductor islands.
2. The method of claim 1 , wherein each of the semiconductor islands comprises a Group IVA element.
3. The method of claim 1 , wherein forming the plurality of semiconductor islands comprises printing the semiconductor ink in a pattern, thereby forming an array of the semiconductor islands.
4. The method of claim 1 , wherein the semiconductor ink comprises a silane in an amount of from 1 to 50 wt. % of the ink and a solvent in which the silane is soluble, the silane having a formula Si x H y , where x is from 3 to 1000, and y is from x to (2x+2), where x may be derived from an average number molecular weight of the silane.
5. The method of claim 1 , further comprising forming gate dielectric layers on or over at least a subset of the plurality of semiconductor islands.
6. The method of claim 5 , further comprising forming a gate on each of the gate dielectric layers.
7. The method of claim 6 , wherein the gate(s) comprise aluminum, silver, gold, copper, palladium, tungsten, platinum, or molybdenum.
8. The method of claim 6 , wherein forming the gate comprises printing a gate precursor ink on the gate dielectric layers.
9. The method of claim 8 , wherein the gate precursor ink comprises metal nanoparticles and a solvent.
10. The method of claim 8 , further comprising removing exposed portions of the gate dielectric layers after forming the gates and prior to printing the dielectric layer.
11. The method of claim 8 , further comprising:
a) forming contact holes in the dielectric layer, exposing (i) at least part of an upper surface of one or more of the gates and (ii) portions of one or more of the semiconductor islands on opposed sides of each of the one or more gate(s); and
b) forming a metal layer in contact with (1) the upper surface(s) of each of the one or more gate(s) and (2) the portions of the one or more semiconductor islands, wherein forming the metal layer comprises printing a metal ink.
12. The method of claim 11 , further comprising annealing the metal layer under conditions sufficient to form a metal silicide at an interface with the semiconductor island.
13. The method of claim 1 , wherein printing the dielectric layer comprises inkjetting, flexographic printing, offset lithographic printing, gravure printing, or screen printing a doped dielectric ink formulation comprising a dielectric precursor, a dopant precursor, and a solvent.
14. The method of claim 13 , wherein the dielectric layer is printed in a pattern on or over the plurality of semiconductor islands and the substrate.
15. The method of claim 13 , wherein the dielectric precursor comprises a precursor of silicon oxide, and the dopant precursor is selected from the group consisting of oxides and oxo compounds of phosphorous, boron, arsenic and antimony.
16. The method of claim 1 , wherein forming the plurality of semiconductor islands comprises curing the semiconductor ink after the semiconductor ink is printed or coated.
17. The method of claim 1 , wherein the annealing is conducted at a temperature and for a length of time sufficient to form source/drain terminals in the semiconductor islands.
18. The method of claim 1 , wherein forming the plurality of semiconductor islands comprises coating the semiconductor ink on the electrically functional substrate and patterning the coated semiconductor ink using low-resolution lithographic patterning.
19. The method of claim 1 , wherein the semiconductor islands are physically isolated from one another.