IP Library Granted Patent US 8,861,257
Granted Patent B2
US 8,861,257 · App. 13/634,700 · Granted Oct 14, 2014

Nonvolatile memory element, manufacturing method thereof, nonvolatile memory device, and design support method for nonvolatile memory element

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Quick Facts
Patent No.
US 8,861,257
App. No.
13/634,700
Granted
Oct 14, 2014
Kind
B2
Abstract

A nonvolatile memory element includes a variable resistance layer located between a lower electrode and an upper electrode and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer includes at least two layers: a first variable resistance layer including a first transition metal oxide; and a second variable resistance layer including a second transition metal oxide and a transition metal compound. The second transition metal oxide has an oxygen content atomic percentage lower than an oxygen content atomic percentage of the first transition metal oxide, the transition metal compound contains either oxygen and nitrogen or oxygen and fluorine, and the second transition metal oxide and the transition metal compound are in contact with the first variable resistance layer.

Claims (46)

1. A nonvolatile memory element comprising:

a first electrode and a second electrode that are formed above a semiconductor substrate; and

a variable resistance layer located between the first electrode and the second electrode and having a resistance value that reversibly changes based on an electric signal applied between the first electrode and the second electrode,

wherein the variable resistance layer comprises at least two layers including a first variable resistance layer and a second variable resistance layer,

the first variable resistance layer has a first face connected to the first electrode,

the first variable resistance layer has a second face connected to a first face of the second variable resistance layer,

the first variable resistance layer comprises a first transition metal oxide,

the second variable resistance layer comprises a second transition metal oxide and a first transition metal compound,

the second transition metal oxide has an oxygen content atomic percentage lower than an oxygen content atomic percentage of the first transition metal oxide,

the first transition metal compound contains either oxygen and nitrogen or oxygen and fluorine and is in contact with at least part of the second face of the first variable resistance layer, and

the second transition metal oxide is in contact with a remaining part of the second face of the first variable resistance layer.

2. The nonvolatile memory element according to claim 1 ,

wherein the second transition metal oxide and the first transition metal compound comprise a same transition metal.

3. The nonvolatile memory element according to claim 1 ,

wherein the second transition metal oxide is disposed in a central region of the second variable resistance layer, and

the first transition metal compound is disposed in a peripheral region of the second variable resistance layer.

4. The nonvolatile memory element according to claim 1 ,

wherein the second transition metal oxide is disposed in a peripheral region of the second variable resistance layer, and

the first transition metal compound is disposed in a central region of the second variable resistance layer.

5. The nonvolatile memory element according to claim 1 ,

wherein the nitrogen or fluorine contained in the first transition metal compound is combined with a dangling bond contained in the first transition metal compound, to terminate the dangling bond.

6. The nonvolatile memory element according to claim 1 ,

wherein the second transition metal oxide and the first transition metal compound are equal in thickness.

7. The nonvolatile memory element according to claim 1 ,

wherein the variable resistance layer further comprises a third variable resistance layer,

the variable resistance layer comprises three layers: the first variable resistance layer; the second variable resistance layer; and the third variable resistance layer,

the third variable resistance layer comprises a third transition metal oxide and a second transition metal compound,

the third transition metal oxide has a resistivity lower than resistivities of the first transition metal oxide and the second transition metal oxide,

the second transition metal compound has a resistivity lower than a resistivity of the first transition metal compound,

the second transition metal compound contains either oxygen and nitrogen or oxygen and fluorine and is in contact with a second face of the first transition metal compound, and

the third transition metal oxide is in contact with a second face of the second transition metal oxide.

8. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory cells each of which includes the nonvolatile memory element according to claim 1 and a switching element which are connected in series;

a selection circuit that selects at least one of the memory cells included in the memory cell array, by turning ON the switching element in the memory cell;

a write circuit that applies a write voltage pulse to the nonvolatile memory element included in the memory cell selected by the selection circuit; and

a sense amplifier that detects an amount of current flowing to the nonvolatile memory element included in the memory cell selected by the selection circuit, to determine data stored in the nonvolatile memory element.

9. A method of supporting design of the nonvolatile memory element according to claim 1 , the method comprising:

calculating a dependency relationship between a size, in a plane direction, of the second transition metal oxide and an initialization voltage of the nonvolatile memory element;

determining the initialization voltage required for a nonvolatile memory element to be designed;

specifying the size, in the plane direction, of the second transition metal oxide, which corresponds to the initialization voltage determined in the determining, with reference to the dependency relationship calculated in the calculating; and

outputting a manufacturing condition which corresponds to the size specified in the specifying.

10. The method according to claim 9 ,

wherein the calculating includes:

manufacturing, on a single substrate, a plurality of nonvolatile memory elements which are different in the size and each of which is the nonvolatile memory element;

initializing, at a different initialization voltage, each of the nonvolatile memory elements manufactured in the manufacturing, to measure the initialization voltage; and

determining the dependency relationship of each of the nonvolatile memory elements by associating the size and the initialization voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2016
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 039860/0960 →