Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device

1. A method of inspecting a variable resistance nonvolatile memory device,

the variable resistance nonvolatile memory device including:

a memory cell array having a plurality of memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of a plurality of word lines and one of a plurality of bit lines, the variable resistance element changing at least between a low resistance state and a high resistance state, and the current steering element carrying a current from which the current steering element is assumed to be conducting as a result of an application of a voltage exceeding a predetermined threshold voltage;

a memory cell selection circuit that selects one of the memory cells by selecting at least one of the word lines and at least one of the bit lines; and

a read circuit that reads a resistance state of the selected memory cell by performing voltage application on the selected memory cell so that a first voltage higher than the threshold voltage and a second voltage lower than the threshold voltage are applied to the current steering element of the selected memory cell, and

the method comprising:

determining that the current steering element has a short-circuit fault in the case where a value of a current passing through the current steering element is higher than or equal to a predetermined value, when the resistance state of the memory cell is read by the application of the second voltage; and

determining whether the variable resistance element is in the low resistance state or the high resistance state, when the resistance state of the memory cell is read by the application of the first voltage.

2. The method of inspecting the variable resistance nonvolatile memory device according to claim 1 ,

wherein the second voltage is lower than the first voltage by the threshold voltage.

3. The method of inspecting the variable resistance nonvolatile memory device according to claim 1 , the method further comprising

writing the low resistance state to the memory cell, before the determining that the current steering element has the short-circuit fault,

wherein, when the current having the value higher than or equal to the predetermined value does not pass through the current steering element, the current steering element is determined to be normal.

4. The method of inspecting the variable resistance nonvolatile memory device according to claim 1 ,

wherein, after the resistance state of the memory cell is read by the application of the second voltage, the resistance state of the memory cell is read by the application of the first voltage.

5. The method of inspecting the variable resistance nonvolatile memory device according to claim 1 ,

wherein the predetermined value is a maximum value of a current passing through the current steering element when (i) the threshold voltage is applied to the current steering element that is normal and in the low resistance state and (ii) the current steering element is assumed to be in an OFF state.

6. A variable resistance nonvolatile memory device comprising:

a plurality of word lines arranged in parallel to each other in a first plane;

a plurality of bit lines that are arranged in parallel to each other in a second plane parallel to the first plane, and three-dimensionally cross the word lines;

a memory cell array having a plurality of memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of the word lines and one of the bit lines, the variable resistance element changing at least between a low resistance state and a high resistance state, and the current steering element carrying a current from which the current steering element is assumed to be conducting as a result of an application of a voltage exceeding a predetermined threshold voltage;

a memory cell selection circuit that selects one of the memory cells by selecting at least one of the word lines and at least one of the bit lines; and

a read circuit that reads a resistance state of the selected memory cell,

wherein the read circuit includes:

a bit-line control voltage generation circuit that (i) generates a first voltage higher than the threshold voltage and a second voltage lower than the threshold voltage and (ii) outputs the first voltage and the second voltage from a first output terminal and a second output terminal, respectively;

a bit-line voltage switching circuit that is connected to the bit-line control voltage generation circuit and switches between the first voltage and the second voltage to provide a corresponding one of the first voltage and the second voltage;

a bit-line voltage steering circuit that has (i) an output terminal connected to the memory cell selection circuit and (ii) a control terminal connected to the bit-line voltage switching circuit; and

a detection circuit that detects a current passing through the selected memory cell via the selected word line and the selected bit line as a result of an application of a voltage to the selected bit line, the voltage being determined according to a voltage to be applied to the control terminal of the bit-line voltage steering circuit,

wherein, when the resistance state of the memory cell is read by the application of the first voltage, the detection circuit provides (i) a first logic output when the selected memory cell is in the low resistance state and (ii) a second logic output when the selected memory cell is in the high resistance state, and

when the resistance state of the memory cell is read by the application of the second voltage and the current steering element of the selected memory cell has a short-circuit fault, the detection circuit provides (i) the first logic output when the variable resistance element is in the low resistance state, and (ii) one of the first logic output and the second logic output when the variable resistance element is in the high resistance state.

7. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the bit-line voltage steering circuit includes an N-channel metal oxide semiconductor (NMOS) transistor,

the output terminal of the bit-line voltage steering circuit is one of a source terminal and a drain terminal of the NMOS transistor, and

the control terminal of the bit-line voltage steering circuit is a gate terminal of the NMOS transistor.

8. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the second voltage is lower than the first voltage by the threshold voltage.

9. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the second voltage is generated as a partial voltage of the first voltage and is higher than a ground potential used as a reference potential, and

the current steering element is connected between the first output terminal and the second output terminal of the bit-line control voltage generation circuit.

10. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the second voltage is generated as a partial voltage of the first voltage and is higher than a ground potential used as a reference potential,

a fixed resistance element is connected between the first output terminal and the second output terminal of the bit-line control voltage generation circuit, and

a resistance value of the fixed resistance element is set so that a potential difference between the first voltage and the second voltage is equal to the threshold voltage.

11. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the second voltage is generated as a partial voltage of the first voltage and is higher than a ground potential used as a reference potential, and

an NMOS transistor and a resistance element are connected in series between the ground potential and the second output terminal of the bit-line control voltage generation circuit, the NMOS transistor having a drain terminal and a gate terminal connected to each other.

12. The variable resistance nonvolatile memory device according to claim 11 ,

wherein the resistance element is formed by a variable resistance element having a same configuration as the variable resistance element included in the memory cell, and is set to one of a low resistance state and a high resistance state.

13. The variable resistance nonvolatile memory device according to claim 11 ,

wherein the resistance element is formed by a fixed resistance element, and

a resistance value of the fixed resistance element is set to be between a resistance value of the variable resistance element in the low resistance state and a resistance value of the variable resistance element in the high resistance state.

14. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the second voltage is generated as a partial voltage of the first voltage and is higher than a ground potential used as a reference potential,

a fixed resistance element is connected between the ground potential and the second output terminal of the bit-line control voltage generation circuit, and

a resistance value of the fixed resistance element is set so that a potential difference between the first voltage and the second voltage is equal to the threshold voltage.

15. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the second voltage is generated as a partial voltage of the first voltage and is higher than a ground potential used as a reference potential, and

a current steering element having a same configuration as the current steering element included in the memory cell and a variable resistance element having a same configuration as the variable resistance element included in the memory cell are connected in series between the first output terminal and the second output terminal of the bit-line control voltage generation circuit.

16. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the bit-line control voltage generation circuit includes a first voltage source generating the first voltage and a second voltage source generating the second voltage.

17. The variable resistance nonvolatile memory device according to claim 6 ,

wherein the read circuit further includes a voltage detection circuit that detects a voltage of the selected bit line.