Programming at least one multi-level phase change memory cell

1. A method for programming at least one multi-level Phase Change Memory, PCM, cell being controllable by a first terminal and a second terminal, comprising:

programming the PCM cell to have a respective definite cell state by at least one current pulse applied to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level,

controlling said respective current pulse by a respective first pulse applied to the first terminal and a respective second pulse applied to the second terminal, and

controlling said respective first pulse and said respective second pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

2. The method of claim 1 , wherein said step of controlling the current pulse is started with an initial pair of a first pulse, in particular a bitline pulse, and a second pulse, in particular a wordline pulse, said initial pair being derived from average programming curves provided in dependence on a plurality of PCM cells.

3. The method of claim 1 , wherein said second pulse is a wordline voltage pulse applied to a control terminal of an access entity for controlling an access to the PCM cell and said first pulse is a bitline voltage pulse applied to the bitline, said PCM cell being coupled between said bitline and said access entity, wherein said wordline voltage pulse and said bitline voltage pulse are controlled by a difference value of the actual resistance value and the reference resistance value.

4. The method of claim 2 , comprising:

dividing at least a part of a resistance window between a lowest and a highest resistance value of the PCM cell into a plurality of distinct resistance ranges,

respectively associating the distinct resistance ranges with a different programming trajectory, said different programming trajectories being respectively defined by a different wordline pulse or by a different bitline pulse,

mapping a respective definite resistance level to one of the distinct resistance ranges, the mapped distinct resistance range having an associated programming trajectory, and

applying iterative programming on the PCM cell in order to achieve the respective definite resistance level using bitline pulses or wordline pulses and the programming trajectory associated to the resistance range on which the respective definite resistance level is mapped.

5. The method of claim 4 , wherein a full-scale resistance window between the lowest and the highest resistance value of the PCM cell is divided into the plurality of distinct resistance ranges.

6. The method of claim 4 , wherein the respective resistance range is associated with the programming trajectory covering the respective definite resistance level and having a maximum resolution of the programming trajectories covering the respective definite resistance level, in particular the respective resistance range is associated with the programming trajectory which is adapted to increase a linearity and/or a width of the programming voltage or current window.

7. The method of claim 4 , wherein the respective programming trajectory is associated with a maximum programming current which is associated with a respective maximum resistance value for limiting the maximum current of the respective current pulse flowing to the PCM cell.

8. The method of claim 4 , wherein said iterative programming is applied on the PCM cell in order to achieve the respective definite resistance level using bitline pulses or wordline pulses of varying amplitude and the programming trajectory associated to the resistance range on which the respective definite resistance level is mapped.

9. The method of claim 1 , comprising:

programming the respective PCM cell to have a respective definite cell state by a number of different current pulses flowing to the PCM cell, said respective definite cell state being defined by at least a number of different definite resistance levels.