IP Library Granted Patent US 9,195,603
Granted Patent B2
US 9,195,603 · App. 13/642,045 · Granted Nov 24, 2015

Storage caching

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,195,603
App. No.
13/642,045
Granted
Nov 24, 2015
Kind
B2
Abstract

The present disclosure provides a method for processing a storage operation in a system with an added level of storage caching. The method includes receiving, in a storage cache, a read request from a host processor that identifies requested data and determining whether the requested data is in a cache memory of the storage cache. If the requested data is in the cache memory of the storage cache, the requested data may be obtained from the storage cache and sent to the host processor. If the requested data is not in the cache memory of the storage cache, the read request may be sent to a host bus adapter operatively coupled to a storage system. The storage cache is transparent to the host processor and the host bus adapter.

Claims (32)

1. A method, comprising:

receiving, in a storage cache, a read request from a storage device driver running on a host processor, wherein the read request identifies requested data;

determining whether the requested data is in a cache memory of the storage cache;

if the requested data is in the cache memory of the storage cache, obtaining the requested data from the storage cache and sending the requested data to the host processor; and

if the requested data is not in the cache memory of the storage cache, sending the read request from a second storage device driver running on the storage cache to a host bus adapter operatively coupled to a storage system by enqueuing the read request in a command queue residing on a memory of the storage cache;

wherein the storage cache is transparent to the host processor and the host bus adapter.

2. The method of claim 1 , comprising, in response to sending the read request to the host bus adapter:

receiving the requested data from the storage system through the host bus adapter; and

writing a copy of the requested data received through the host bus adapter to the cache memory of the storage cache.

3. The method of claim 1 , comprising:

writing data to the cache memory of the storage cache; and

writing a backup copy of the data to a second cache memory of a second storage cache operatively coupled to the host processor.

4. The method of claim 1 , comprising:

receiving, in the storage cache, a write command from the host processor that includes payload data to be stored to the storage system;

writing the payload data to the cache memory of the storage cache; and

passing the write command to the host bus adapter.

5. A system, comprising:

a storage cache operatively coupled to a host processor, the storage cache configured to receive storage operations from the host processor and process the storage operations in accordance with a cache allocation policy implemented by the storage cache; and

a host bus adapter coupled to the storage cache and configured to receive the storage operations from the host processor through the storage cache based on a result of the processing of the storage operations in the storage cache;

wherein a processor of the storage cache interfaces with a storage device driver running on the host processor, and the processor of the storage cache runs a second storage device driver for interfacing with the host bus adapter so that the storage cache is transparent to the host processor and the host bus adapter; and

wherein the storage cache comprises a command queue and the host bus adapter is configured to obtain storage operations from the command queue of the storage cache.

6. The system of claim 5 , wherein the storage cache and the host bus adapter are integrated in the same component packaging to form a caching host bus adapter, the storage cache comprises a local storage cache of the caching host bus adapter, and the host bus adapter comprises a host bus adapter core.

7. The system of claim 5 , wherein the storage cache is a separate storage caching device operatively coupled between the host processor and the host bus adapter and operatively coupled to the host bus adapter through an I/O bus.

8. The system of claim 5 , comprising a second storage cache operatively coupled between the host processor and a second host bus adapter, the storage cache configured to replicate caching operations to the second storage cache.

9. The system of claim 5 , comprising a solid state drive operatively coupled to the host processor, the storage cache configured to save a backup copy of a cache memory of the storage cache to the solid state drive.

10. A non-transitory computer readable memory comprising code configured to direct a processor to:

receive a storage operation from a storage device driver running on a host processor;

if the storage operation is a write command with payload data, write the payload data to a cache memory and send the write command to a host bus adapter via a second storage device driver running on a storage cache;

if the storage operation is a read request, determine whether the requested data is in the cache memory; and

if the requested data is in the cache memory, receive the data from the cache memory and send the requested data to the host processor; and

if the requested data is not in the cache memory, send the read request to the host bus adapter via the second storage device driver running on the storage cache enqueuing the read request in a command queue residing on a memory of the cache memory.

11. The non-transitory computer readable memory of claim 10 , comprising code configured to direct the processor to store a backup copy of the cache memory to a second storage cache operatively coupled to the host processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2012
From: PRICE, JEFFREY A
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 029165/0381 →