Three-dimensional integrated circuit and testing method for the same
View Patent ↗Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.
1. A chip among a plurality of chips to be layered into a three-dimensional integrated circuit, the chip comprising:
a plurality of connections for electrical connection with an adjacent chip among the plurality of chips;
a plurality of test signal generation circuits each configured to output a test signal; and
a plurality of test result judgment circuits each configured to receive a signal from an external source and, in accordance with a state of the signal, to detect a conducting state of a transmission path for the signal, wherein
one each of the plurality of test signal generation circuits and the plurality of test result judgment circuits correspond with a pair of connections that are adjacent among the plurality of connections,
one of the plurality of test signal generation circuits corresponding with the pair of connections outputs the test signal to one of the pair of connections, and
one of the plurality of test result judgment circuits corresponding with the pair of connections receives the signal from the other one of the pair of connections.
2. The chip of claim 1 , wherein
the pair of connections is composed of a first connection and a second connection,
the chip further comprising:
a switch circuit configured to switch between
a state of connecting one of the plurality of test signal generation circuits corresponding with the pair of connections to the first connection and connecting one of the plurality of test result judgment circuits corresponding with the pair of connections to the second connection, and
a state of connecting one of the plurality of test result judgment circuits corresponding with the pair of connections to the first connection and connecting one of the plurality of test signal generation circuits corresponding with the pair of connections to the second connection.
3. The chip of claim 1 , wherein
the plurality of connections is located in a grid in a first region, and
the plurality of test signal generation circuits and the plurality of test result judgment circuits are located in a zigzag lattice pattern in second regions that extend along either side of the first region.
4. A three-dimensional integrated circuit in which a plurality of chips are layered,
each of the plurality of chips comprising:
a plurality of connections for electrical connection with an adjacent chip among the plurality of chips;
a plurality of test signal generation circuits each configured to output a test signal; and
a plurality of test result judgment circuits each configured to receive a signal from an external source and, in accordance with a state of the signal, to detect a conducting state of a transmission path for the signal, wherein
one each of the plurality of test signal generation circuits and the plurality of test result judgment circuits correspond with a pair of connections that are adjacent among the plurality of connections,
one of the plurality of test signal generation circuits corresponding with the pair of connections outputs the test signal to one of the pair of connections, and
one of the plurality of test result judgment circuits corresponding with the pair of connections receives the signal from the other one of the pair of connections.
5. The three-dimensional integrated circuit of claim 4 , wherein
connections adjacent along a normal line between two adjacent chips among the plurality of chips are electrically connected to each other.
6. The three-dimensional integrated circuit of claim 4 , wherein
before the plurality of chips are layered, each of the plurality of test result judgment circuits in one of the plurality of chips receives a signal arising from the test signal output by one of the plurality of test signal generation circuits in the same chip, and
after the plurality of chips are layered, each of the plurality of test result judgment circuits in one of the plurality of chips receives a signal arising from the test signal output by one of the plurality of test signal generation circuits in another chip.
7. The chip of claim 2 , wherein
the plurality of connections is located in a grid in a first region, and
the plurality of test signal generation circuits and the plurality of test result judgment circuits are located in a zigzag lattice pattern in second regions that extend along either side of the first region.
8. The three-dimensional integrated circuit of claim 5 , wherein
before the plurality of chips are layered, each of the plurality of test result judgment circuits in one of the plurality of chips receives a signal arising from the test signal output by one of the plurality of test signal generation circuits in the same chip, and
after the plurality of chips are layered, each of the plurality of test result judgment circuits in one of the plurality of chips receives a signal arising from the test signal output by one of the plurality of test signal generation circuits in another chip.