Supply power dependent controllable write throughput for memory applications
View Patent ↗Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput.
1. A method of managing throughput in a memory device, comprising:
monitoring a power supply level;
determining an appropriate memory write throughput based on a number of cells to which the memory device can write at a time at the monitored power supply level;
generating a control signal based on the determined memory write throughput, wherein the control signal is configured to cause a driver circuit to activate a portion of a memory array consistent with said determined memory write throughput.
2. The method of claim 1 , wherein monitoring the power supply level comprises receiving an indication of voltage level value of the power supply from a voltage level detector.
3. The method of claim 1 , wherein the driver circuit comprises a plurality of transistors, wherein each of the plurality of transistors is configured to provide power to a corresponding bitline in the memory array.
4. The method of claim 3 , wherein each of the plurality of transistors is configured to: provide power to a corresponding bitline when in an ON state; and not provide power to the corresponding bitline when in an OFF state.
5. The method of claim 3 , wherein the control signal is configured to toggle the state of a set of the plurality of transistors.
6. The method of claim 5 , wherein the set comprises fewer than all of the plurality of transistors.
7. The method of claim 1 , wherein the appropriate memory write throughput is determined using a look-up table.
8. The method of claim 7 , wherein the look-up table is programmable.
9. The method of claim 1 , further comprising:
detecting a reduction in the power supply level;
determining a reduced memory write throughput; and
adjusting the control signal to deactivate a portion of the memory array consistent with the determined reduced memory write throughput.
10. The method of claim 1 , further comprising:
detecting an increase in the power supply level;
determining an increased memory write throughput; and
adjusting the control signal to activate an additional portion of the memory array consistent with the determined increased memory write throughput.
11. The method of claim 1 , wherein the memory array comprises NOR Flash memory.
12. A memory device, comprising:
a memory array comprising a plurality of memory cells;
a controller configured to:
monitor a power supply level,
determine an appropriate memory write throughput based on a number of cells to which the memory device can write at a time at the monitored power supply level, and
generate a control signal based on the determined memory write throughput; and
a driver circuit configured to selectively drive portions of the memory array based on a received control signal.
13. The device of claim 12 , wherein the controller is configured to monitor the power supply level by receiving an indication of the current voltage level of the power supply from a voltage level detector.
14. The device of claim 12 , wherein the driver circuit comprises a plurality of transistors, wherein each of the plurality of transistors is configured to provide power to a corresponding bitline in the memory array.
15. The device of claim 14 , wherein each of the transistors are configured to provide power to a corresponding bitline when in an ON state; and not provide power to the corresponding bitline when in an OFF state.
16. The device of claim 14 , wherein the control signal is configured to toggle the state of a set of the transistors.
17. The device of claim 16 , wherein the set comprises fewer than all of the plurality of transistors.
18. The device of claim 12 , wherein the appropriate memory write throughput is determined using a look-up table.
19. The device of claim 18 , wherein the look-up table is programmable.
20. The device of claim 12 , wherein the controller is further configured to:
detect a reduction in the power supply level;
determine a reduced memory write throughput; and
adjust the control signal to deactivate a portion of the memory array consistent with the determined reduced memory write throughput.
21. The device of claim 12 , wherein the controller is further configured to:
detect an increase in the power supply level;
determine an increased memory write throughput; and
adjust the control signal to activate an additional portion of the memory array consistent with the determined increased memory write throughput.
22. The device of claim 12 , wherein the memory array comprises NOR Flash memory.