Configurable serial interface

1. A configurable serial interface comprising:

a configuration node;

one or more input nodes each coupled to a respective serial bus;

one or more output nodes each coupled to a respective serial bus;

at least one driver configured to drive a respective output node;

a voltage detection circuit coupled to the configuration node and operative to detect a voltage at the configuration node, wherein:

the configurable serial interface is operative to set a mode of serial bus operation based on the voltage detected at the configuration node; and

in at least one mode of serial bus operation, the configuration node is configured both as a mode select input and a power source for at least one driver of an output node.

2. The configurable serial interface of claim 1 , wherein the configuration node is:

(i) coupled to a ground;

(ii) coupled to a VDDLOGIC voltage level; or

(iii) floating.

3. The configurable serial interface of claim 1 , wherein:

in a first mode of serial bus operation, the at least one output driver of an output node is configured to provide an output voltage substantially equal to the voltage at the configuration node; and

in a second mode of serial bus operation, the at least one output driver of an output node is configured as an open drain.

4. The configurable serial interface of claim 3 , wherein:

the first mode of serial bus operation is Serial Peripheral Interface (SPI), and

the second mode of serial bus operation is I 2 C.

5. The configurable serial interface of claim 3 wherein when in a second mode of serial bus operation:

a first output node is operative as a serial data input and output (SDA) pin;

a first input node is operative as a serial clock input (SCL) pin;

a second input node is operative as a first address select input (AS1); and

a third input node is operative as a second address select input (AS2).

6. The configurable serial interface of claim 1 , wherein a logic threshold level is based on the voltage at the configuration node.

7. The configurable serial interface of claim 1 , further comprising at least one input buffer, each input buffer having an input coupled to a respective input node.

8. The configurable serial interface of claim 7 , wherein the at least one input buffer is configured as a Schmitt Trigger.

9. The configurable serial interface of claim 1 , further comprising a float detection circuit coupled to at least one input node.

10. The configurable serial interface of claim 1 , further comprising a float detection circuit coupled to the configuration node.

11. The configurable serial interface of claim 1 , wherein the voltage detection circuit comprises:

a pull-down transistor having its drain coupled to the configuration node and its source coupled to a first voltage node;

a state machine coupled to a gate of the pull-down transistor; and

a level detector coupled between the drain of the pull-down transistor and the state machine.

12. The configurable serial interface of claim 11 , wherein the level detector comprises an inverter having a PMOS and an NMOS.

13. The configurable serial interface of claim 1 , further comprising a digital logic circuit having one or more state machines.

14. A method of configuring a serial interface having at least one output driver, the method comprising:

determining a voltage at a configuration pin;

when the determined voltage is within a first range, entering a first mode of serial bus operation, comprising:

using the voltage at the configuration pin as a mode select input; and

using the voltage at the configuration pin as a power supply for the least one output driver; and

when the determined voltage is within a second range, entering a second mode of serial bus operation, comprising:

configuring the output driver as an open drain.

15. The method of claim 14 , wherein:

the first mode of serial bus operation is Serial Peripheral Interface (SPI), and

the second mode of serial bus operation is I 2 C.

16. The method of claim 14 , wherein entering a second mode of serial bus operation comprises:

configuring a first output node as a serial data input and output (SDA);

configuring a first input node as a serial clock input (SCL);

configuring a second input node as a first address select input (AS1); and

configuring a third input node as a second address select input (AS2).

17. The method of claim 14 , further comprising adjusting a logic threshold level based on the voltage of the configuration pin.

18. The method of claim 14 , further comprising determining whether the configuration pin is floating.

19. The method of claim 14 , further comprising determining whether an address select input is floating.