High-speed long codeword QC-LDPC soft decision decoder
View Patent ↗A Quasi-Cyclic, LDPC, large girth, soft-decision decoder and accompanying methods.
1. A high speed long codeword decoder comprising:
a plurality of pipelined stages including an input stage and an output stage communicatively coupled to a plurality of intermediate stages, wherein said input stage is configured to receive an input vector and convert it to a C-node processing sequence, said intermediate stages configured to perform C-node to V-node conversion, V-node operation, and V-node to C-node conversion, and said output stage being configured to perform V-node to output sequence conversion;
computer executable code to execute a Check-To-Variable Message Passing code, where each check node c computes the check-to-variable message R CV with variable-to-check message L CV as
R
CV
=
∏
n
∈
N
(
c
)
\
v
sign
(
L
CN
)
×
Ψ
{
∑
n
∈
N
(
c
)
\
v
Ψ
(
L
CN
)
}
where
Ψ
(
β
)
=
ln
(
e
β
+
1
e
β
-
1
)
.
and computer executable code to perform Variable-to-check Message Passing, wherein each variable node v computes the variable-to-checkmessage L CV with check-to-variable message R CV ,
L CV =Σ mεM(v)\c R mv +I v .
2. The high speed long codeword decoder of claim 1 further configured such that each one of the pipelined stages is effected in one iteration of operation.
3. The high speed long codeword decoder of claim 2 further configured such that all of the V-nodes (variable node) process all column circulants in parallel and within each circulant column V-nodes are grouped into a single processing cycle.
4. The high speed long codeword decoder of claim 3 further configured such that all of the C-nodes (check node) process all row circulants in parallel and within each circulant row C-nodes are grouped into a single processing cycle.
5. The high speed long codeword decoder of claim 4 wherein from check node output to variable node input, there exist three processing stages to change node order for processing.
6. The high speed long codeword decoder of claim 5 wherein from variable node output to check node input there exist three processing stages to change node order for processing.
7. The high speed long codeword decoder of claim 5 wherein the three processing stages include a first multiplexer matrix, a buffer and a second multiplexer matrix.
8. The high speed long codeword decoder of claim 6 wherein the three processing stages include a first multiplexer matrix, a buffer matrix and a second multiplexer matrix.
9. The high speed long codeword decoder of claim 7 wherein the first multiplexer matrix comprises at least one 2:1 multiplexer.
10. The high speed long codeword decoder of claim 9 wherein the 2:1 multiplexer is only used for those nodes involving a last processing group.
11. The high speed long codeword decoder of claim 10 wherein the second multiplexer matrix comprises at least one 2:1 multiplexer and that multiplexer is only used for those nodes involving a last processing group.
12. The high speed long codeword decoder of claim 11 wherein the buffer matrix is interposed between check node output and variable node input and variable node output and check node input.
13. The high speed long codeword decoder of claim 12 wherein the buffer matrix is allocated such that write access conflict is prevented.