Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same
View Patent ↗Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.
1. A semiconductor device comprising:
a data terminal;
a calibration terminal;
a first transistor unit coupled to the data terminal, the first transistor unit including a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable;
a plurality of second transistor units coupled to the calibration terminal, each of the second transistor units including a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable using an impedance code; and
an impedance control circuit reflecting the impedance of each of the second transistor units to the first transistor unit.
2. The semiconductor device as claimed in claim 1 , wherein a plurality of the first transistor units are coupled in parallel to the data terminal.
3. The semiconductor device as claimed in claim 2 , further comprising a mode register selecting a number of the first transistor units to be activated among the plurality of the first transistor units.
4. The semiconductor device as claimed in claim 1 , wherein the impedance control circuit adjusts the impedance of each of the second transistor units to be equal in value based on a potential of the calibration terminal.
5. The semiconductor device as claimed in claim 4 , wherein the impedance control circuit adjusts the impedance of each of the second transistor units by individually controlling the second transistors included in each of the second transistor units.
6. The semiconductor device as claimed in claim 1 , further comprising:
a first resistor element coupled between the data terminal and the first transistor unit; and
a plurality of second resistor elements each coupled between the calibration terminal and an associated one of the second transistor units,
wherein the first resistor element and each of the second resistor elements are substantially the same in a resistance value as each other.
7. The semiconductor device as claimed in claim 1 , wherein the second transistor units are connected in parallel to the calibration terminal.
8. The semiconductor device as claimed in claim 1 , wherein the second transistor units are connected in series to the calibration terminal.
9. The semiconductor device as claimed in claim 1 , further comprising:
a third transistor unit coupled to the data terminal, the third transistor unit including a plurality of third transistors having a second conductivity type connected in parallel to each other so that an impedance of the third transistor unit is adjustable; and
a fourth transistor unit including a plurality of fourth transistors having the second conductivity type connected in parallel to each other so that an impedance of the fourth transistor units is adjustable,
wherein the impedance control circuit adjusts the impedance of the fourth transistor unit with reference to the impedance of each of the second transistor units, and reflects the impedance of the fourth transistor unit to the third transistor unit.
10. The semiconductor device as claimed in claim 9 , wherein the second transistor units and the fourth transistor unit are different in number from each other.
11. A semiconductor device comprising:
a data terminal;
a calibration terminal;
a first power supply line supplied with a first power supply potential;
a first transistor unit coupled between the first power supply line and the data terminal;
a plurality of second transistor units coupled between the first power supply line and the calibration terminal, wherein each second transistor unit of the plurality of second transistor units comprises a plurality of transistors, and the plurality of second transistor units are connected in parallel to each other so that an impedance of each of the second transistor units is adjustable using an impedance code; and
an impedance control circuit adjusting the impedance of each of the second transistor units so that a potential of the calibration terminal matches with a reference potential, the impedance control circuit reflecting the impedance of one of the second transistor units to the first transistor unit.
12. The semiconductor device as claimed in claim 11 , further comprising:
a second power supply line supplied with a second power supply potential;
a third transistor unit coupled between the second power supply line and the data terminal;
a fourth transistor unit coupled between the second power supply line and an internal node; and
a plurality of fifth transistor units coupled between the first power supply line and the internal node,
wherein the impedance control circuit reflects the impedance of each of the second transistor units to each of the fifth transistor units, adjusts an impedance of the fourth transistor unit so that a potential of the internal node matches with the reference potential, and reflects the impedance of the fourth transistor unit to the third transistor unit.
13. The semiconductor device as claimed in claim 11 , wherein the reference potential is different in potential level from an intermediate potential between the first power supply potential and the second power supply potential.
14. A semiconductor device comprising:
a first terminal;
a second terminal supplied with a reference voltage;
one or more first transistor units, each of the first transistor units including a plurality of first transistors of a first conductivity type, the first transistors of each of the first transistor units being coupled in parallel to the first terminal and being respectively controlled in response to first calibration signals;
one or more second transistor units, each of the second transistor units including a plurality of second transistors of a second conductivity type, the second transistors of each of the second transistor units being coupled in parallel to the first terminal and being respectively controlled in response to second calibration signals; and
an impedance control circuit coupled to the first and second terminals, and being configured to compare an electrical potential of the first terminal with the reference potential of the second terminal to generate the second calibration signals;
a number of the first transistor units being different from a number of the second transistor units.
15. The semiconductor device as claimed in claim 14 , further comprising:
a calibration terminal; and
one or more third transistor units each of the third transistor units including a plurality of third transistors of the first conductivity type, the third transistors of each of the third transistor units being coupled in parallel to the calibration terminal and being respectively controlled in response to the first calibration signals;
wherein the impedance control circuit is coupled to the second terminal and the calibration terminal and configured to compare an electrical potential of the calibration terminal with the reference potential of the second terminal to generate the first calibration signals.
16. The semiconductor device as claimed in claim 15 , wherein a number of the third transistor units is equal to the number of the first transistor units.
17. The semiconductor device as claimed in claim 15 , further comprising:
a data terminal;
a plurality of fourth transistor units, each of the fourth transistor units including a plurality of fourth transistors of the first conductivity type, the fourth transistors of each of the fourth transistor units being coupled in parallel to the data terminal and being controlled in response to the first calibration signals; and
a plurality of fifth transistor units, each of the fifth transistor units including a plurality of fifth transistors of the second conductivity type, the fifth transistors of each of the fifth transistor units being coupled in parallel to the data terminal and being controlled in response to the second calibration signals.
18. The semiconductor device as claimed in claim 17 , wherein a number of the fourth transistor units is equal to a number of the fifth transistor units.
19. The semiconductor device as claimed in claim 17 , wherein the first transistor unit is replicate of the fourth transistor unit and the second transistor unit is replicate of the fifth transistor unit.