Method of schematic driven layout creation
View Patent ↗A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively.
1. A computer-implemented method of generating a layout for a circuit design, the method comprising:
receiving a schematic of the circuit design, the circuit design comprising a plurality of sub-circuits, wherein each of the plurality of sub-circuits comprises a plurality of instances arranged according to a topology representing relative positions of the plurality of instances;
generating a layout pattern for each sub-circuit in one portion of the schematic;
selecting a first layout pattern of a first sub-circuit from said one portion of the schematics;
identifying, by using a computer, at least one sub-circuit in another portion of the schematic based on the difference between the topology of the identified sub-circuit and the topology of the first sub-circuit being within a pre-defined tolerance, wherein each instance of the identified sub-circuit has a corresponding instance in the first sub-circuit; and
copying the first layout pattern to generate a layout pattern for the at least one identified sub-circuit,
wherein the difference between the topology of the identified sub-circuit and the topology of the first sub-circuit satisfies the following:
Δ x ij =x i −x j , ΔX ij =X i −X j ,
Δ y ij =y i −y j , ΔY ij =Y i −Y j ,
|Δ x ij −ΔX ij |≦Δx×p ,
|Δ y ij −ΔY ij |≦Δy×p ,
wherein x i , x j , y i , and y j are the X and Y coordinates of two instances in the topology of the identified sub-circuit; X i ,X j , Y i , and Y j are the X and Y coordinates of the corresponding instances in the topology of the first sub-circuit; Δx and Δy are the X span and Y span of the topology of the identified sub-circuit; and p is a pre-defined constant.
2. The computer-implemented method according to claim 1 , wherein p is zero, such that the topology of the identified sub-circuit and the topology of the first sub-circuit are identical.
3. The computer-implemented method according to claim 1 , wherein the difference between the topology of the identified sub-circuit and the topology of the first sub-circuit is determined by comparing a one dimensional mirror of the topology of the identified sub-circuit with the topology of the first sub-circuit.
4. The computer-implemented method according to claim 3 , wherein said one dimensional mirror of the topology of the identified sub-circuit is relative to x axis or y axis.
5. The computer-implemented method according to claim 1 , wherein the difference between the topology of the identified sub-circuit and the topology of the first sub-circuit is determined by comparing a two dimensional mirror of the topology of the identified sub-circuit with the topology of the first sub-circuit.
6. The computer-implemented method according to claim 5 , wherein said two dimensional mirror of the topology of the identified sub-circuit is relative to x and y axes.
7. The computer-implemented method according to claim 1 , wherein the difference between the topology of the identified sub-circuit and the topology of the first sub-circuit is determined by rotating the topology of the identified sub-circuit and comparing the rotated topology of the identified sub-circuit with the topology of the first sub-circuit.
8. The computer-implemented method according to claim 1 , wherein a graphic user interface is provided to display the at least one sub-circuit along with the difference between the topology of the at least one sub-circuit and the topology of the first sub-circuit.
9. The computer-implemented method according to claim 1 , wherein the at least one sub-circuit and the first sub-circuit are analog circuits.
10. The computer-implemented method according to claim 1 , wherein the layout of the circuit is for an integrated circuit (IC).
11. The computer-implemented method according to claim 1 , wherein the layout of the circuit design is for a printed circuit board (PCB).