Substrate bias feedback scheme to reduce chip leakage power

1. A method, comprising:

generating a control signal based on a difference between a leakage current of a baseline circuit and a reference signal;

supplying the control signal to an analog control input of a voltage generation circuit to set a value of a reverse body bias voltage output from the voltage generation circuit; and supplying the reverse body bias voltage to a body of the baseline circuit, wherein the reference signal is a reference current derived from a reference voltage.

2. The method of claim 1 , further comprising:

comparing the reverse body bias voltage to the reference signal and based on the comparison selectively disabling the voltage generation circuit.

3. The method of claim 1 , further comprising:

applying the reverse body bias voltage to a chip substrate.

4. The method of claim 1 , wherein the baseline circuit comprises a transistor, and the voltage generation circuit applies the bias voltage to a well of the transistor.

5. The method of claim 1 , wherein the control bias voltage is generated by varying a potential based on a difference between a current capacity of a current source and a current capacity of the baseline circuit.

6. The method of claim 1 , further comprising limiting the reverse body bias voltage to a maximum voltage.

7. The method of claim 1 , further comprising coupling a gate and a source-drain path of the baseline circuit between a current source and a first power supply node.

8. The method of claim 7 , wherein the current source comprises a source transistor having a conductivity type different from a conductivity type of the baseline circuit and a source-drain path of the source transistor is coupled to the baseline circuit, and wherein the method further comprises receiving at a terminal of the source transistor a reference bias signal.

9. The method of claim 1 , wherein the setting the value of the reverse body bias voltage output comprises controlling a charge pump.

10. An apparatus, comprising:

a baseline circuit;

a control circuit coupled with the baseline circuit, configured to generate a control signal based on a difference between a leakage current of the baseline circuit and a reference signal, wherein the reference signal is a reference current derived from a reference voltage; and

a voltage generator circuit configured receive the control signal at an analog control input and to supply a reverse body bias voltage to a body of the baseline circuit.

11. The apparatus of claim 10 , wherein the voltage generator comprises a charge pump circuit comprising:

at least one charge pump cell configured to generate the reverse body bias voltage in response to a control clock signal; and

an analog clock driver configured to vary the control clock signal in response to the difference between the reference signal and a current through the baseline circuit.

12. The apparatus of claim 10 , wherein the voltage generator is coupled with a chip substrate, and wherein the voltage generator is further configured to apply the reverse body bias voltage to the chip substrate.

13. The apparatus of claim 11 , wherein the baseline circuit comprises a transistor, and wherein the charge pump circuit is further configured to apply the bias voltage to a well of the transistor.

14. The apparatus of claim 10 , wherein the control circuit comprises:

an amplifier having an input coupled with the baseline circuit; and

a compare node coupled with an output of the amplifier, wherein the amplifier is configured to generate the control bias voltage by varying a potential of the compare node based on a difference between a current capacity of a current source and a current capacity of the baseline circuit.

15. The apparatus of claim 10 , wherein the control circuit further comprises a voltage to current converter configured to convert the reference voltage to the reference current.

16. The apparatus of claim 10 , wherein the control circuit further comprises a feedback circuit including a clamp circuit coupled with the voltage generator, wherein the clamp circuit is configured to limit the reverse body bias voltage to a maximum voltage.

17. The apparatus of claim 10 , wherein the baseline circuit has a gate and a source-drain path coupled between a current source and a first power supply node.

18. An apparatus, comprising:

a baseline circuit;

a control circuit coupled with the baseline circuit, wherein the control circuit is configured to generate a control bias signal based on a difference between a leakage current of the baseline circuit and a reference signal;

a voltage generator coupled with the baseline circuit, wherein the voltage generator is configured to output a reverse body bias voltage applied to a body of the baseline circuit based on the control bias signal from the amplifier circuit; and

a clamp circuit configured to limit the reverse body bias voltage to a maximum value.

19. The apparatus of claim 18 , wherein the clamp circuit is configured to compare the reverse body bias voltage to the reference signal and based on the comparison to selectively disable the voltage generator.